Datasheet > NG80960KB-25

NG80960KB-25

更新时间： 2024-09-18 23:53:35

品牌	Logo	应用领域
其他 - ETC		外围集成电路装置时钟
页数	文件大小	规格书
44页	416K
描述
MICROPROCESSOR\|32-BIT\|CMOS\|QFP\|132PIN\|PLASTIC

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NG80960KB-25 数据手册

80960KB

EMBEDDED 32-BIT MICROPROCESSOR

WITH INTEGRATED FLOATING-POINT UNIT

■ High-Performance Embedded

■ Built-in Interrupt Controller

Architecture

— 25 MIPS Burst Execution at 25 MHz

— 31 Priority Levels, 256 Vectors

— 3.4 µs Latency @ 25 MHz

— 9.4 MIPS* Sustained Execution at

25 MHz

■ Easy to Use, High Bandwidth 32-Bit Bus

— 66.7 Mbytes/s Burst

■ 512-Byte On-Chip Instruction Cache

— Up to 16 Bytes Transferred per Burst

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

■ 132-Lead Packages:

— Pin Grid Array (PGA)

— Plastic Quad Flat-Pack (PQFP)

■ Multiple Register Sets

■ On-Chip Floating Point Unit

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip

— Supports IEEE 754 Floating Point

Standard

— Four 80-Bit Registers

— 13.6 Million Whetstones/s (Single

Precision) at 25 MHz

— Register Scoreboarding

■ 4 Gigabyte, Linear Address Space

■ Pin Compatible with 80960KA

FOUR

80-BIT FP

REGISTERS

64- BY 32-BIT

LOCAL

CACHE

SIXTEEN

32-BIT GLOBAL

REGISTERS

32-BIT

INSTRUCTION

EXECUTION

UNIT

80-BIT

FPU

32-BIT

BUS CONTROL

LOGIC

MICRO-

INSTRUCTION

SEQUENCER

512-BYTE

INSTRUCTION

CACHE

MICRO-

INSTRUCTION

ROM

32-BIT

BURST

BUS

INSTRUCTION

FETCH UNIT

INSTRUCTION

DECODER

Figure 1. The 80960KB Processor’s Highly Parallel Architecture

June, 1997

Order Number: 270565.007

12 3 4 5 6 7...44

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