NCP51190, NCV51190
1.5A DDR Memory
Termination Regulator
The NCP/NCV51190 is a simple, cost−effective, high−speed linear
regulator designed to generate the V termination voltage rail for
TT
DDR−I, DDR−II and DDR−III memory. The regulator is capable of
actively sourcing or sinking up to 1.5 A for DDR−I, or up to 0.5 A
for DDR−II /−III while regulating the output voltage to within
30 mV.
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MARKING
DIAGRAM
The output termination voltage is tightly regulated to track V
=
TT
(V
/ 2) over the entire current range.
DDQ
1
DFN8
The NCP/NCV51190 incorporates a high−speed differential
amplifier to provide ultra−fast response to line and load transients.
Other features include extremely low initial offset voltage, excellent
load regulation, source/sink soft−start and on−chip thermal shut−down
protection.
XXMG
MN SUFFIX
CASE 506AA
G
1
XX = Specific Device Code
M
= Date Code
The NCP/NCV51190 features the power−saving Suspend To Ram
(STR) function which will tri−state the regulator output and lower the
quiescent current drawn when the /SS pin is pulled low.
The NCP/NCV51190 is available in a DFN8 package.
G
= Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTION
Features
• Generate DDR Memory Termination Voltage (V
)
TT
• For DDR−I, DDR−II, DDR−III Source / Sink Currents
• Supports DDR−I to 1.5 A, DDR−II, DDR−III to 0.5 A (peak)
• Integrated Power MOSFETs with Thermal Protection
• Stable with 10 mF Ceramic V Capacitor
TT
• High Accuracy Output Voltage at Full−Load
• Minimal External Component Count
• Shutdown for Standby or Suspend to RAM (STR) mode
• Built−in Soft Start
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 8 of this data sheet.
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These are Pb−Free Devices
Appications
• Desktop PC’s, Notebooks, and Workstations
• Graphics Card DDR Memory Termination
• Set Top Boxes, Digital TV’s, Printers
• Embedded Systems
• Active Bus Termination
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2014 − Rev. 3
NCP51190/D