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NCP51199PDR2G PDF预览

NCP51199PDR2G

更新时间: 2024-02-22 16:46:11
品牌 Logo 应用领域
安森美 - ONSEMI PC双倍数据速率光电二极管接口集成电路
页数 文件大小 规格书
8页 80K
描述
DDR 2-Amp Source / Sink VTT Termination Regulator

NCP51199PDR2G 技术参数

是否无铅:不含铅生命周期:Active
包装说明:HSOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:4 weeks风险等级:1.42
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:226233Samacsys Pin Count:9
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:SOIC-8 NB EP CAST 751BU ISSUEBSamacsys Released Date:2015-08-19 02:35:14
Is Samacsys:N接口集成电路类型:BUS TERMINATOR SUPPORT CIRCUIT
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:3
功能数量:1端子数量:8
封装主体材料:PLASTIC/EPOXY封装代码:HSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG
座面最大高度:1.75 mm表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

NCP51199PDR2G 数据手册

 浏览型号NCP51199PDR2G的Datasheet PDF文件第2页浏览型号NCP51199PDR2G的Datasheet PDF文件第3页浏览型号NCP51199PDR2G的Datasheet PDF文件第4页浏览型号NCP51199PDR2G的Datasheet PDF文件第5页浏览型号NCP51199PDR2G的Datasheet PDF文件第6页浏览型号NCP51199PDR2G的Datasheet PDF文件第7页 
NCP51199, NCV51199  
DDR 2-Amp Source / Sink  
VTT Termination Regulator  
The NCP/NCV51199 is a linear regulator designed to supply a  
regulated V termination voltage for DDR−2 and DDR−3 memory  
TT  
applications. The regulator is capable of actively sourcing and sinking  
2 A peak currents for DDR−2, and DDR−3 up to 1.5 A while  
www.onsemi.com  
regulating the V output voltage to within 10 mV. The output  
TT  
MARKING  
DIAGRAM  
termination voltage is regulated to track V  
/ 2 by two external  
DDQ  
voltage divider resistors connected to the PV , GND, and V  
pins.  
CC  
REF  
8
The NCP/NCV51199 incorporates a high−speed differential  
amplifier to provide ultra−fast response to line and load transients.  
Other features include source/sink current limiting, soft−start and  
on−chip thermal shutdown protection.  
XXXXXX  
ALYW  
G
SOIC8−NB EP  
PD SUFFIX  
CASE 751BU  
8
1
1
Features  
Supports DDR−2 V Termination to 2 A, DDR−3 to 1.5 A (peak)  
TT  
XXXXXX = Specific Device Code  
A
L
= Assembly Location  
= Wafer Lot  
Stable with 10 mF Ceramic Capacitance on V Output  
TT  
Integrated Power MOSFETs  
Y
= Year  
WW  
G
= Work Week  
= Pb−Free Package  
High Accuracy V Output at Full−Load  
TT  
Fast Transient Response  
Built−in Soft−Start  
Shutdown for Standby or Suspend Mode  
Integrated Thermal and Current−Limit Protection  
NCV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
PIN CONNECTION  
1
8
PVCC  
NC  
NC  
GND  
VREF  
V
CC  
These Devices are Pb−Free and are RoHS Compliant  
V
TT  
NC  
SOIC−8 EP  
Typical Applications  
SDRAM Termination Voltage for DDR−2 / DDR−3  
Motherboard, Notebook, and VGA Card Memory Termination  
Set Top Box, Digital TV, Printers  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information in the  
package dimensions section on page 6 of this data sheet.  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
April, 2017 − Rev. 3  
NCP51199/D  

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