Datasheet > MX98723UC

MX98723UC

更新时间： 2024-01-30 19:02:52

品牌	Logo	应用领域
旺宏电子 - Macronix		时钟局域网数据传输 PC 外围集成电路
页数	文件大小	规格书
47页	243K
描述
LAN Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP144, LQFP-144

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MX98723UC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP, QFP144(UNSPEC)
针数：	144	Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01	风险等级：	5.92
地址总线宽度：	32	边界扫描：	NO
总线兼容性：	PCI; CARDBUS	最大时钟频率：	20 MHz
最大数据传输速率：	12.5 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
低功率模式：	YES	串行 I/O 数：	1
端子数量：	144	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP144(UNSPEC)
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Serial IO/Communication Controllers
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN	Base Number Matches：	1

MX98723UC 数据手册

ADVANCED INFORMATION

MX98723UC

PCI/CARDBUS FAST ETHERNET CONTROLLER

1.0 Feature

• A 32-bit CardBus/PCI fast Ethernet Controller inte-

grates 10/100 Base-T MAC, NWAY, MII Interface and

10 Base-T transceiver

• Compliant to CardBus specification of the PC Card

Standard 6.1

• Compliant to PCI specification Revision 2.2 and PCI

Bus Power Management Interface specification Revi-

sion 1.0

• FullycomplytoIEEE802.3andANSI8802_3Ethernet

standards.

• 32-bitbusmasterDMA channelprovidesultralowCPU

utilization

• Support upto256KB bootROMandFLASHinterface

Also, support a single latch on the boot ROM port

• Three levels of loopback diagnostic capability

• Support a variety of flexible address filtering modes

with 16 CAM addresses and 512 bits hash

• Support CardBus Card Information Structure (CIS)

body stored in a 4k-bit Serial EEPROM or Flash ROM

• MicroWire interface to Serial EEPROM containing

Subsystem ID, Card Information Structure (CIS)

pointer, Ethernet address and so on

• Support full duplex operation on both MII/SYM and 10

Base-T ports

• Support 802.3x "Frame Based Flow Control" scheme

in full duplex mode

• Support network and communication device class

OnNow requirements for Microsoft's PC98 specifica-

tions, including all wake-up events:

1. Magic Packet^TM

• Support PCI/CardBus unlimit burst, read line, read

multiple, write and invalidate commands

• SupportLEDoutputforvariousnetworkactivityindica-

tions

• Support early interrupt on transmit and receive

• SupportCardBusclockcontrolthroughCLKRUNBpin

• SupportCardBusCSTSCHGpinandStatusChanged

registers

2. Wake-up Frames

3. Link Change

• Support 10 Mb/s and 100 Mb/s NWAY auto negotia-

tion function

• Large on chip FIFOs for both transmit and receive

operations without external local memory

• Bus master architecture with linked host buffers deliv-

ers world class performance

• 3.3V operating power

• 144-pin LQFP package with standard CMOS technol-

ogy

( Magic Packet^TMTechnology is a trademark of Ad-

vanced Micro Device Corp. )

2.0 Genernal Description

The MX98723UC, 10/100M media access controller, with

3.3V PCI/CardBus interface is an optimized design to

ease interface with CSMA/CD type local area networks

including 100Mb/s-TX/FX Fast Ethernet, 10Mb/s Thick

Ethernet, 10Mb/sThin Ehternet (Cheapernet), StarLAN

with external network transceivers and 10MbpsTwisted-

pair Ethernet without external transceiver. High speed

PCI/CardBus master interface is implemented to sup-

port 100Mb/s fast Ethernet with fast packet buffer man-

agement. On chip control registers and PCI/CardBus

configuration registers provide interface to host system

for automatic bus master configuration and driver con-

trols.As a PCI/CardBus bus master, MX98723UC incor-

porates large on chip FIFOs which provides effective

local packet buffers, therefore no external local buffer

memory is needed.

The MX98723UC implements all Media Access Control

(MAC) layer functions for transmission, reception and

NWAY auto-negociation in accordance with the IEEE

802.3/802.3u standard. MX98723UC can be programmed

to support various level of interconnects. Supported in-

terconnects are standard Media Independent Interface

( MII ) ,100Base-TX Physical Coding Sublayer ( PCS

),and a direct 10Base Twisted pair media interface.

Full duplex and half duplex are both supported for differ-

ent applications. A packet buffer is located in the host

memory that is used by software driver for all incoming

and outgoing packets.This buffer area is shared by both

transmit process and receive process.During reception,

the MX98723UC stores packets in the receive buffer area,

then indicates receive status and control information in

P/N:PM0487

REV. 0.7, JUN. 22, 2000

12 3 4 5 6 7...47

中文翻译

下载PDF

与MX98723UC相关器件

型号	品牌	获取价格	描述	数据表
MX98725	ETC	获取价格	SINGLE CHIP FAST ETHERNET NIC CONTROLLER
MX98726	Macronix	获取价格	SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE
MX98726AEC	ETC	获取价格	Controller Miscellaneous - Datasheet Reference
MX98726EC	Macronix	获取价格	SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE
MX98727	ETC	获取价格	SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
MX98727BEC	Macronix	获取价格	LAN Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP128, PLASTIC, LQFP-128
MX98728	ETC	获取价格	GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
MX98728AEC	ETC	获取价格	Controller Miscellaneous - Datasheet Reference
MX98728EC	Macronix	获取价格	GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
MX98741	Macronix	获取价格	XRC 100 BASE-TX/FX REPEATER CONTROLLER

与MX98723UC相关文章

MBRS340T3G手册解读：参数说明、产品特性及应用
2024-06-28

7
PMOS管背靠背连接：串联还是并联？
2024-06-28

7
高压电解电容的分类与选型策略
2024-06-28

8
数码管：基本概念、分类、技术发展及市场趋势
2024-06-27

14

产品中心

服务支持

精选活动

关于我们

帮助中心

MX98723UC

MX98723UC 技术参数

MX98723UC 数据手册

与MX98723UC相关器件

与MX98723UC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MX98723UC

MX98723UC 技术参数

MX98723UC 数据手册

与MX98723UC相关器件

与MX98723UC相关文章

您还可以找

您在本页遇到什么问题？