MX98728AEC
GMAC
SINGLECHIP10/100FASTETHERNETCONTROLLER
FORGENERICAPPLICATION
1.0 Features
• 1.6KBTX FIFO to support maximum network through-
put in the full duplex mode
• 16/8 bits SRAM interface of the packet buffer sup-
porting burst DMA for on-chip FIFOs
• 32 bits general purpose asynchronous bus architec-
ture up to 33Mhz for easy system application
• Single chip solution integrating 10/100TP transceiver
to reduce overall cost
• Flexible packet buffer partition and addressing space
for up to 1MB
• NWAY autonegotiation function to automatically set
up network speed and protocol
• Optional MII interface for external tranceiver.
• Fully compliant with the IEEE 802.3u spec.
• Supports 32/16 bits x1, x2, x4 burst read transfers
for the receive packet buffer
• 3 loop back modes for system level diagnosis
• Supports 64 bits hash table for multicast addressing,
broadcast control, optional password check on
multicast frames
• Packet buffer access through an IO mapped port or
host DMA for a wide variety of bus applications
• Programmable bus integrity check timer and interrupt
assertion scheme
• Optional EEPROM configuration, supports 1K bits and
4K bits EEPROM interface
• Supports 16/8 bits packet buffer data width and 32/
16 bits host bus data width
• Supports software EEPROM interface for easy up-
grade of EEPROM contents
• 5V CMOS in an 160 PQFP package
• Separated TX and RX FIFOs to support the full du-
plex mode, independentTX and RX channel
• Rich on-chip registers to support a wide variety of
network management functions
1.1 Introduction
MX98728AEC ( GMAC ) is a general purpose single chip
10/100 Fast Ethernet controller.With no glue logic or very
little extra logic, it can be used in a variety of system
applications through its host bus interface. Single chip
solution will help reduce system cost, not only on the IC
count but also on the board size. Full NWAY function
with 10/100 transceiver will ease the field installation.
Simply plug the chip in and it will connect itself with the
best protocol available.
A programmable receive packet interrupt scheme using
a timer (RXINTT) and a packet counter (RXINTC) allows
system developers to adjust the interrupt traffic.The re-
ceive interrupt assertion timing is also programmable
for different system applications. A general purpose host
receive packet counter (HRPKTCNT) is also provided to
the host for the buffer management purpose.
Bus integrity check feature allows the system to recover
from a bus hang or an excessively long bus access.
BICT ( Bus integrity check timer ) can be programmed
to abort any bus access that runs abnormally long. Pass-
word based multicast and broadcast frame filtering is
supported to minimize the unnecessary network traffic.
A data cache is also used on the host bus to deliver the
32 /16 bits burst read on the host data port up to 4 data
transfers in a single cycle. Two hand shake signals to
communicate to the host bus interface during the data
port transfer are simple and fast for the system integra-
tor. An intelligent built-in SRAM bus arbiter will manage
all SRAM access requests from the host bus access,
the transmit local DMA and the receive local DMA.
MX98728AEC is also equipped with the back-to-back
transmit capability which allows the software to fire as
many transmit packets as needed in a single command.
The receive FIFO also allows the back-to-back recep-
tion. Optional EEPROM can be used to store the MAC
ID and the other configuration information. All options
including MAC ID can be programmed through the host
interface.
The 16/8 bit SRAM interface with local DMAs help sys-
tem developers to optimize the performance. The be-
havior of these local DMAs can be easily adjusted by
the optional bits on the chip. (The term "packet buffer"
and "packet memory" are used interchangeably in this
document).
P/N:PM0720
REV. 1.0, JUL. 13, 2000
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