5秒后页面跳转
MX98726 PDF预览

MX98726

更新时间: 2024-02-20 08:33:22
品牌 Logo 应用领域
旺宏电子 - Macronix 控制器以太网局域网(LAN)标准以太网:16GBASE-T
页数 文件大小 规格书
55页 287K
描述
SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

MX98726 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:128
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.84地址总线宽度:20
边界扫描:NO总线兼容性:80186; 80188
最大时钟频率:40 MHz最大数据传输速率:12.5 MBps
外部数据总线宽度:16JESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
低功率模式:NO串行 I/O 数:1
端子数量:128最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装形状:RECTANGULAR
封装形式:FLATPACK, FINE PITCH认证状态:Not Qualified
座面最大高度:3.5 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

MX98726 数据手册

 浏览型号MX98726的Datasheet PDF文件第2页浏览型号MX98726的Datasheet PDF文件第3页浏览型号MX98726的Datasheet PDF文件第4页浏览型号MX98726的Datasheet PDF文件第5页浏览型号MX98726的Datasheet PDF文件第6页浏览型号MX98726的Datasheet PDF文件第7页 
ADVANCED INFORMATION  
MX98726  
SINGLE CHIP 10/100 FAST ETHERNET  
CONTROLLER WITH uP INTERFACE  
1.0 Features  
• Support bus size configuration:  
• Direct interface to 80188/186 up to 40Mhz.  
• Integrated 10/100 TP tranceiver on chip to reduce  
overall cost  
- CPU : 8 bits, SRAM: 8 bits  
- CPU : 16 bits, SRAM: 8/16 bits  
• Flexiblepacketbufferpartitionandaddressingspace  
for 32k, 64k up to 512 bytes  
• NWAY autonegociation function to automatically set  
up network speed and protocol  
• 3 loop back modes for system level diagnostics  
• Rich on-chip register set to support a wide variety of  
network management functions  
• Support 64 bits hash table for multicast addressing  
• Support software EEPROM interface for easy up-  
grade of EEPROM content  
• Fully comply to IEEE 802.3u spec.  
• Best fit in network printer and hub/switch manage-  
ment application  
• A local DMA channel between on-chip FIFOs and  
packet memory  
• Shared memory architecture allow host and  
MX98726 to use only one single SRAM  
• Host DMA can share packet memory with local DMA  
with simple hand shake protocol for x188/186 type of  
processor  
• Support 1K bits and 4K bits EEPROM interface  
• 5V CMOS in 128 PQFP package for minimum board  
size application  
1.1 Introduction  
A intelligent built-in SRAM bus arbitor will manage all  
the SRAM access requests from host, on-chip transmit  
channel and on-chip receive channel. The throughput  
of these network channels and MX98726's DMA burst  
length can be easily adjusted by option bits on the chip.  
These options can help system developers to "fine tune"  
a best cost/performance ratio.  
MX98726 ( Generic MAC , or GMAC ) is a cost effective  
solution as a generic single chip 10/100 Fast Ethernet  
controller.It is designed to directly interface 80188, 80186  
( host ) without glue logic.Two types of memory sharing  
schemes are supported, i.e.interleaved and shared mode  
to support a variety of applications. Single chip solution  
will help reduce system cost not only on the compo-  
nents but also the board size. Full NWAY function with  
10/100 tranceiver will ease the field installation, simply  
plug the chip in and it will connect itself with the best  
protocol available.  
MX98726 is also equipped with fast back-to-back trans-  
mit capability which allow software to "fire" as many  
transmit packets as needed in a single command. Re-  
ceive FIFO also allow back-to-back reception. Optional  
EEPROM can be used to stored network network ad-  
dress and other information.In case cost is really a con-  
cern, most configuration options including network ad-  
dress can be programmed through uP.  
The interleaved mode allow uP to access SRAM (  
packet/host buffer ) through MX98726's local DMA chan-  
nel. This way, no extra SRAM interface logic is needed  
on the host side. If high performance is desired, then  
shared memory mode is another alternative which allow  
host to access SRAM on its own by denying SRAM bus  
grant to MX98726 using simple hand shake protocol.  
Without SRAM bus grant, MX98726 will float its inter-  
face connected to the SRAM, therefore host can utilize  
its own memory subsystem to conduct its own SRAM  
access.  
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.  
P/N:PM0555  
REV. 0.9.8, FEB. 14, 2000  
1

与MX98726相关器件

型号 品牌 描述 获取价格 数据表
MX98726AEC ETC Controller Miscellaneous - Datasheet Reference

获取价格

MX98726EC Macronix SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

获取价格

MX98727 ETC SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER

获取价格

MX98727BEC Macronix LAN Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP128, PLASTIC, LQFP-128

获取价格

MX98728 ETC GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

获取价格

MX98728AEC ETC Controller Miscellaneous - Datasheet Reference

获取价格