Datasheet > MX26L6419TC-10

MX26L6419TC-10

更新时间： 2024-11-22 03:15:39

品牌	Logo	应用领域
旺宏电子 - Macronix		存储
页数	文件大小	规格书
45页	436K
描述
64M [x16] SINGLE 3V PAGE MODE MTP MEMORY

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中文翻译

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MX26L6419TC-10 数据手册

ADVANCED INFORMATION

MX26L6419

64M[x16] SINGLE3VPAGEMODEMTPMEMORY

FEATURES

• 3.0V to 3.6V operation voltage

• Block Structure

Software Feature

• Support Common Flash Interface (CFI)

- MTP device parameters stored on the device and

provide the host system to access.

- 64 x 64Kword Erase Blocks

• Fast random / page mode access time

- 100/25 ns Read AccessTime (page depth:8-word)

• 128-bit Protection Register

Hardware Feature

- 64-bit Unique Device Identifier

- 64-bit User Programmable OTP Cells

• 16-WordWrite Buffer

• ACC pin

- 12V VPP for fast program/erase mode.

• VPEN pin

- 14 us/word Effective Programming Time

- For Erase /Program/ Block Lock enable.

• Enhanced Data Protection Features Absolute Protec-

tion with VPEN = GND

• VCCQ Pin

-The output buffer power supply, control the device 's

- Flexible Block Locking

- Block Erase/Program Lockout during PowerTransi-

tions

output voltage.

• RESET pin

- Hardware reset

Performance

• Low power dissipation

Packaging

- 48-LeadTSOP

- typical 15mA active current for page mode read

- 80uA/(max.) standby current

• High Performance

Technology

- Two bits per cell Nbit (0.25u) MTPTechnology

- Block erase time: 2s typ.

- Word programming time:210us typ.

- Block programming time: 0.8s typ. (using Write to

Buffer Command)

• Program/Erase Endurance cycles: 100 cycles

electrical erasure and programming.The device uses a

command register to manage this functionality.

GENERAL DESCRIPTION

The MXIC's MX26L6419 series MTP use the most ad-

vance 2 bits/cell Nbit technology, double the storage ca-

pacity of memory cell.The device provide the high den-

sity MTP memory solution with reliable performance and

most cost-effective.

The MXIC's Nbit technology reliably stores memory con-

tents even after the specific erase and program cycles.

The MXIC cell is designed to optimize the erase and

program mechanisms by utilizing the dielectric's charac-

ter to trap or release charges from ONO layer.

The device organized as by 16 bits of output bus. The

device is packaged in 48-Lead TSOP. It is designed to

be reprogrammed and erased in system or in standard

EPROM programmers.

The device uses a 3.0V to 3.6V VCC supply to perform

the High Reliability Erase and auto Program/Erase algo-

rithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

The device offers fast access time and allowing opera-

tion of high-speed microprocessors without wait states.

The device augment EPROM functionality with in-circuit

P/N:PM0946

REV. 0.3, OCT. 08, 2003

12 3 4 5 6 7...45

中文翻译

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与MX26L6419TC-10相关器件

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MX26L6420	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
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MX26L6420MI-12	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420MI-90	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420TC-12	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420TC-90	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420TI-12	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
MX26L6420TI-90	Macronix	获取价格	64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM

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