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MX26LV004TQC-55 PDF预览

MX26LV004TQC-55

更新时间: 2024-11-22 03:26:39
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旺宏电子 - Macronix 闪存存储内存集成电路
页数 文件大小 规格书
43页 460K
描述
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY HIGH SPEED eLiteFlashTM MEMORY

MX26LV004TQC-55 数据手册

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MX26LV004T/B  
Macronix NBitTM Memory Family  
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE  
3V ONLY HIGH SPEED eLiteFlashTM MEMORY  
FEATURES  
• Extended single - supply voltage range 3.0V to 3.6V  
• 524,288 x 8  
• Status Reply  
- Data# polling & Toggle bit for detection of program  
anderaseoperationcompletion.  
• Ready/Busy# pin (RY/BY#)  
-Providesahardwaremethodofdetectingprogramor  
eraseoperationcompletion.  
• Singlepowersupplyoperation  
- 3.0V only operation for read, erase and program  
operation  
• Fast access time: 55/70ns  
• Lowpowerconsumption  
• 2,000 minimum erase/program cycles  
• Latch-up protected to 100mA from -1V to VCC+1V  
• Package type:  
- 30mA maximum active current  
- 30uA typical standby current  
• Commandregisterarchitecture  
- Byte Programming (55us typical)  
- Sector Erase (Sector structure 16K-Byte x1,  
8K-Byte x2, 32K-Byte x1, and 64K-Byte x7)  
• Auto Erase (chip & sector) and Auto Program  
-Automaticallyeraseanycombinationofsectorswith  
Erase Suspend capability.  
- 40-pin TSOP  
-32-pinPLCC  
• Compatibility with JEDEC standard  
- Pinout and software compatible with single-power  
supply Flash  
• 20 years data retention  
- Automatically program and verify data at specified  
address  
GENERAL DESCRIPTION  
The MX26LV004T/B is a 4-mega bit Flash memory orga-  
nized as 512K bytes of 8 bits. MXIC's Flash memories  
offer the most cost-effective and reliable read/write non-  
volatile random access memory. The MX26LV004T/B is  
packaged in 40-pin TSOP. It is designed to be repro-  
grammed and erased in system or in standard EPROM  
programmers.  
TTL level control inputs and fixed power supply levels  
during erase and programming, while maintaining maxi-  
mum EPROM compatibility.  
MXIC Flash technology reliably stores memory contents  
even after 2,000 erase and program cycles. The MXIC  
cell is designed to optimize the erase and programming  
mechanisms. In addition, the combination of advanced  
tunnel oxide processing and low internal electric fields  
for erase and program operations produces reliable cy-  
cling. The MX26LV004T/B uses a 3.0V~3.6VVCC sup-  
ply to perform the High Reliability Erase and auto Pro-  
gram/Erase algorithms.  
The standard MX26LV004T/B offers access time as fast  
as 55ns, allowing operation of high-speed microproces-  
sors without wait states. To eliminate bus contention,  
the MX26LV004T/B has separate chip enable (CE#) and  
output enable (OE#) controls.  
MXIC's Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
MX26LV004T/B uses a command register to manage  
this functionality. The command register allows for 100%  
The highest degree of latch-up protection is achieved  
with MXIC's proprietary non-epi process. Latch-up pro-  
tection is proved for stresses up to 100 milliamps on  
address and data pin from -1V to VCC + 1V.  
P/N:PM1099  
REV. 1.0, NOV. 08, 2004  
1

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