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MTP15N06VL PDF预览

MTP15N06VL

更新时间： 2024-11-15 22:29:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
8页 218K
描述
TMOS POWER FET 15 AMPERES 60 VOLTS RDS(on) = 0.085 OHM

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MTP15N06VL 技术参数

生命周期：Transferred包装说明：FLANGE MOUNT, R-PSFM-T3
Reach Compliance Code：unknown风险等级：5.31
Is Samacsys：N其他特性：LOGIC LEVEL COMPATIBLE, AVALANCHE RATED
雪崩能效等级（Eas）：113 mJ外壳连接：DRAIN
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：60 V
最大漏极电流 (Abs) (ID)：15 A最大漏极电流 (ID)：15 A
最大漏源导通电阻：0.085 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：110 pFJEDEC-95代码：TO-220AB
JESD-30 代码：R-PSFM-T3JESD-609代码：e0
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：175 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：FLANGE MOUNT极性/信道类型：N-CHANNEL
功耗环境最大值：60 W最大功率耗散 (Abs)：60 W
最大脉冲漏极电流 (IDM)：53 A认证状态：Not Qualified
子类别：FET General Purpose Power表面贴装：NO
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子位置：SINGLE晶体管应用：SWITCHING
晶体管元件材料：SILICON最大关闭时间（toff）：300 ns
最大开启时间（吨）：260 nsBase Number Matches：1

MTP15N06VL 数据手册

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Order this document  
by MTP15N06VL/D  
SEMICONDUCTOR TECHNICAL DATA  
N–Channel Enhancement–Mode Silicon Gate  
TMOS POWER FET  
TMOS V is a new technology designed to achieve an on–resis-  
tance area product about one–half that of standard MOSFETs. This  
new technology more than doubles the present cell density of our  
50 and 60 volt TMOS devices. Just as with our TMOS E–FET  
designs, TMOS V is designed to withstand high energy in the  
avalanche and commutation modes. Designed for low voltage, high  
speed switching applications in power supplies, converters and  
power motor controls, these devices are particularly well suited for  
bridge circuits where diode speed and commutating safe operating  
areas are critical and offer additional safety margin against  
unexpected voltage transients.  
15 AMPERES  
60 VOLTS  
R
= 0.085 OHM  
DS(on)  
TM  
D
New Features of TMOS V  
•
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
DS(on)  
Faster Switching than E–FET Predecessors  
G
•
Features Common to TMOS V and TMOS E–FETS  
S
•
•
•
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and TMOS E–FET  
CASE 221A–06, Style 5  
TO–220AB  
I
DSS  
DS(on)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Drain–to–Source Voltage  
V
DSS  
Vdc  
Vdc  
Drain–to–Gate Voltage (R  
= 1.0 MΩ)  
Gate–to–Source Voltage — Continuous  
V
DGR  
60  
GS  
V
± 15  
± 25  
Vdc  
Vpk  
GS  
Gate–to–Source Voltage — Non–repetitive (t ≤ 10 ms)  
V
GSM  
p
Drain Current — Continuous  
Drain Current — Continuous @ 100°C  
Drain Current — Single Pulse (t ≤ 10 µs)  
I
I
15  
12  
53  
Adc  
D
D
I
Apk  
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
60  
0.40  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
stg  
–55 to 175  
113  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 5.0 Vdc, Peak I = 15 Apk, L = 1.0 mH, R = 25 Ω)  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
R
R
2.5  
62.5  
°C/W  
°C  
θJC  
θJA  
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds  
T
260  
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
REV 1  
Motorola, Inc. 1996  
12345678

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