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MTA9ASF1G72AZ-3G2 PDF预览

MTA9ASF1G72AZ-3G2

更新时间: 2024-04-09 19:00:14
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镁光 - MICRON /
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26页 481K
描述
MTA9ASF1G72AZ – 8GB

MTA9ASF1G72AZ-3G2 数据手册

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8GB (x72, ECC, SR) 288-Pin DDR4 UDIMM  
Pin Descriptions  
Table 5: Pin Descriptions (Continued)  
Symbol  
Type  
Description  
TDQS_t  
TDQS_c  
Output  
Termination data strobe: When enabled via the mode register, the DRAM device enables the  
same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.  
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin provides the da-  
ta mask (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in  
the mode register for both the x4 and x16 configurations. The DM function is supported only in  
x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are enabled/disabled by  
mode register settings. For more information about TDQS, see the DDR4 DRAM component da-  
ta sheet (TDQS_t and TDQS_c are not valid for UDIMMs).  
(x8 DRAM-based  
RDIMM only)  
VDD  
VPP  
Supply  
Supply  
Supply  
Supply  
Supply  
Supply  
Module power supply: 1.2V (TYP).  
DRAM activating power supply: 2.5V –0.125V/+0.250V.  
Reference voltage for control, command, and address pins.  
Ground.  
VREFCA  
VSS  
VTT  
Power supply for termination of address, command, and control VDD/2.  
Power supply used to power the I2C bus for SPD.  
Reserved for future use.  
VDDSPD  
RFU  
NC  
No connect: No internal electrical connection is present.  
No function: May have internal connection present, but has no function.  
NF  
CCMTD-1725822587-9938/09005aef864bc2a8  
asf9c1gx72az.pdf – Rev. F 05/2021 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
8
© 2015 Micron Technology, Inc. All rights reserved.  

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