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MT933/CG/TP1N PDF预览

MT933/CG/TP1N

更新时间: 2024-01-19 01:49:00
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
18页 143K
描述
Ethernet Transceiver, CMOS, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64

MT933/CG/TP1N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TFQFP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.91
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm功能数量:1
端子数量:64最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.2 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

MT933/CG/TP1N 数据手册

 浏览型号MT933/CG/TP1N的Datasheet PDF文件第1页浏览型号MT933/CG/TP1N的Datasheet PDF文件第3页浏览型号MT933/CG/TP1N的Datasheet PDF文件第4页浏览型号MT933/CG/TP1N的Datasheet PDF文件第5页浏览型号MT933/CG/TP1N的Datasheet PDF文件第6页浏览型号MT933/CG/TP1N的Datasheet PDF文件第7页 
MT933  
48 MINT  
47 DVDD3  
46 MDC  
SUBGND2 1  
TX_ER 2  
DGND1 3  
45 MDIO  
TX_EN 4  
44 DGND3  
43 RefCLK  
42 OSCVDD  
41 XTAL1  
40 XTAL2  
39 OSCGND  
38 TXGND4  
37 TXVDD4  
36 TXREF100  
35 TXREF10  
34 TXVDD3  
33 TXGND3  
LNKST 5  
ACTST 6  
COLST 7  
DVDD1 8  
RXVDD3 9  
RXGND3 10  
FDST 11  
SPDST 12  
PA4 13  
RESETN 14  
RXVDD2 15  
RXGND2 16  
TP64  
Figure 2Pin connections  
10Base-T Operation  
Functional Description  
The MT933 has three basic modes of operation:  
10BASE-T, 100BASE-TX and LOW POWER modes.  
The Control block is designed to manage these  
modes by starting and stopping the 10M and 100M  
transceivers in a well-controlled manner such that no  
spurious signals are output on either the MII or  
twisted-pair interfaces. Furthermore, it continuously  
monitors the behaviour of the transceivers and takes  
corrective action if a fault is detected.  
10Mb/s Data Transfer on the MII  
10Mb/s data is transferred across the MII with clock  
speeds of 2.5MHz. The MAC outputs data to the  
MT933 via the MII interface, on the TXD[3:0] bus.  
This data is synchronised to the rising edge of  
TX_CLK. To indicate that there is valid data for  
transmission on the MII, the MAC sets the TX_EN  
signal active. This forces the MT933 device to take in  
the data on the TXD[3:0] bus. This is serialised and  
directly encoded as Manchester data, before being  
output on the TXOP/TXON differential output for  
transmission through 1:Ö2 magnetics and onto the  
twisted-pair.  
Other modes described herein are repeater mode  
and reset mode.  
25MHz Reference Clock  
The transmit current is governed by the current through  
the TXREF10 pin, which must be grounded through  
a resistor as described in “External Components”.  
The MT933 requires a 25MHz +/-100ppm timing  
reference for 802.3 compatible operation. This may  
be supplied either from the integrated oscillator or  
from an external source. When the integrated oscillator  
is used, a suitable crystal must be connected across  
the XTAL1 & XTAL2 pins (see “External Components”)  
and REFCLK must be tied low. When an external  
source is used, it must be input to the REFCLK pin  
and XTAL1 must be tied low. XTAL2 must be  
unconnected.  
RX10 Clock Recovery  
The MT933 employs a digital delay line controlled by  
the 100MHz Synthesizer DLL to derive a sampling  
clock from the incoming signal. The recovered clock  
runs at twice the data rate (nominally 20MHz). When  
a signal is received from the Signal Detect block, it is  
used to strobe Link Pulses and Manchester encoded  
serial data.  
2

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