Datasheet > MT933/CG/TP1N

MT933/CG/TP1N

更新时间： 2024-02-06 18:29:42

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
18页	143K
描述
Ethernet Transceiver, CMOS, PQFP64, 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64

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MT933/CG/TP1N 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	TFQFP,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.91
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	功能数量：	1
端子数量：	64	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

MT933/CG/TP1N 数据手册

MT933

Initialization (RESET_N)

TX_EN TX_ER

TXD [3:0]

ignored

Indication

The MT933 incorporates a power-on-reset circuit for

self-initialization on power-up. During initialization

the open-drain RESET_N pin is driven low and all

data outputs are disabled to prevent spurious outputs

to the twisted-pair and to the MII interface. RESET_N

will remain low until the power supply has been stable

for at least 400ns. The MT933 will then release

RESET_N allowing the external pull-up to pull the pin

high. Device initialisation will not commence until

RESET_N is high. This allows the user to extend the

inactive period by externally holding RESET_N low.

It will not normally be necessary for the user to reset

the MT933 because it is designed to automatically

recover from fault conditions. However, if required,

the user may initialize the device by doing a hardware

or software reset.

Normal inter frame data

0000 through 1111 Normal data transmission

0000 through 1111 Transmit error propagation

Figure 3. 100Mb/s Transmit Error States

100Mb/s Receive Errors

When there is no data on the cable, the receiver will

see only the idle code of scrambled 1’s. If a non idle

symbol is detected, the receiver looks for the SSD so

that it can align the incoming message for decoding.

If any 2 non consecutive zeros are detected within 10

bits, but are not the SSD symbols a false carrier

indication is signalled to the MII by asserting RX_ER

and setting RXD[3:0] to 1110 whilst keeping RX_DV

inactive. The remainder of the message is ignored

until 10 bits of 1’s are detected.

Reset Mode

There are two types of reset in the MT933 - hardware

and software. The hardware reset is activated by

setting the RESET_N pin to logic 0, and holding it low

for at least 100ns. This mode causes an over-all reset

in the MT933 - both analog and digital circuitry are

reset. Whilst RESET_N is low, the SPDST and FDST

pins are inputs, and are used to determine the speed

and duplex capability which will be advertised during

auto-neg. A low on SPDST advertises 100M capability.

A high on FDST advertises full duplex capability.

If any data is decoded after a SSD which is neither a

valid data code nor an ESD, then an error is flagged

by setting RX_ER active whilst the RX_DV signal is

active. This also happens if 2 idle codes are detected

before a valid ESD has been received or descramble

synchronisation is lost during packet reception. The

states of RX_DV and RX_ER are summarised in

Figure 4. RX_ER is clocked on the falling edge of

RX_CLK, and will remain active for at least 1 period

of RX_CLK.

The software reset is activated by setting bit 15 in

a partial reset of the device.

RX_DV RX_ER

RXD [3:0]

0000 through 1111 Normal inter frame

1110 False carrier indication

0000 through 1111 Normal data reception

0101 or 0110 Data reception with errors

Indication

Figure 5 summarises the different blocks to be reset

and which reset will affect them:

Block

HW Reset

yes

SW reset

yes

management register

PCS state machine (RCV,

XMT, ANEG)

yes

Figure 4. 100Mb/s receive error states

XMT scrambler

RCV scramble

control state machine

analog

yes

CONTROLS

Initialization, mode selection and other options are

governed by the control inputs and register as

described in the following paragraphs.

Figure 5. Effects of Reset

Note: Holding RESET_N low will hold the device in a static,

low power state.

1 2 3 456 7 8...18

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MT93L00AV	ZARLINK	Multi-Channel Voice Echo Canceller	获取价格
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