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MT89L85AP1 PDF预览

MT89L85AP1

更新时间: 2024-02-23 08:46:04
品牌 Logo 应用领域
美高森美 - MICROSEMI PC电信电信集成电路
页数 文件大小 规格书
25页 592K
描述
Digital Time Switch, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44

MT89L85AP1 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:NJESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.585 mm
湿度敏感等级:3功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.585 mmBase Number Matches:1

MT89L85AP1 数据手册

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MT89L85  
Data Sheet  
Pin Description  
Pin #  
Name  
Description  
44  
48 SSOP  
PLCC  
23  
24  
R/W Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a  
microprocessor access.  
24  
26  
CS Chip Select (Input). Active low input enabling a microprocessor read or write of control  
register or internal memories.  
25-27  
29-33  
34  
27-29 D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data in the  
31-35  
internal control register, connect memory high, connect memory low and data memory.  
VSS Ground Rail.  
1,25,37  
35-39  
41-43  
38-42  
44-46  
STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These streams are  
STo0 composed of 32 channels at data rates of 2.048 Mbit/s.  
44  
47  
ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If  
this input is low STo0-7 are high impedance. If this input is high each channel may still be put  
into high impedance by software control.  
1
48  
CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits  
per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect  
Memory high locations.  
6,18, 6,19,30,4 NC No Connection.  
28,40  
3
Functional Description  
With the integration of voice, video and data services into the same network, there has been an increasing demand  
for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported  
through time slot interchange circuits. Existing requirements demand time slot interchange devices performing  
switching with constant throughput delay while guaranteeing minimum delay for voice channels.  
The MT89L85 device provides both functions and allows existing systems based on the MT8985 to be easily  
upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to  
switch 64 kbit/s PCM or N x 64 kbit/s data. The MT89L85 can provide both frame integrity for data applications and  
minimum throughput switching delay for voice applications on a per channel basis.  
By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per  
channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces  
through the ST-BUS interface. Different digital backplanes can be accepted by the MT89L85 device without user's  
intervention. The MT89L85 device provides an internal circuit that automatically identifies the polarity and format of  
frame synchronization input signals compatible to ST-BUS and GCI interfaces.  
Device Operation  
A functional block diagram of the MT89L85 device is shown in Figure 1. The serial ST-BUS streams operate  
continuously at 2.048 Mb/s and are arranged in 125 µs wide frames each containing 32 8-bit channels. Eight input  
(STi0-7) and eight output (STo0-7) serial streams are provided in the MT89L85 device allowing a complete 256 x  
256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as  
required in ST-BUS and GCI specifications.  
3
Zarlink Semiconductor Inc.  

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