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MT89L85AP1 PDF预览

MT89L85AP1

更新时间: 2024-02-06 10:34:47
品牌 Logo 应用领域
美高森美 - MICROSEMI PC电信电信集成电路
页数 文件大小 规格书
25页 592K
描述
Digital Time Switch, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44

MT89L85AP1 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:NJESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.585 mm
湿度敏感等级:3功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.585 mmBase Number Matches:1

MT89L85AP1 数据手册

 浏览型号MT89L85AP1的Datasheet PDF文件第4页浏览型号MT89L85AP1的Datasheet PDF文件第5页浏览型号MT89L85AP1的Datasheet PDF文件第6页浏览型号MT89L85AP1的Datasheet PDF文件第8页浏览型号MT89L85AP1的Datasheet PDF文件第9页浏览型号MT89L85AP1的Datasheet PDF文件第10页 
MT89L85  
Data Sheet  
the ODE input pin is LOW. If ME bit is HIGH, then the MT89L85 behaves as if bits 2 (Message Channel) and 0  
(Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value.  
If ME bit is LOW, then bit 2 and 0 of each Connect Memory HIGH location operates normally. In this case, if bit 2 of  
the CMH is HIGH, the associated ST-BUS output channel is in Message mode. If bit 2 of the CMH is LOW, then the  
contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an  
output.  
If the ODE input pin is LOW, then all serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable)  
of the CMH location enables (if HIGH) or disables (if LOW) the output drivers for the corresponding individual ST-  
BUS output stream and channel.  
The contents of bit 1 (CSTo) of each Connection Memory High location (see Figure 5) is output on CSTo pin once  
every frame. The CSTo pin is a 2048 Mbit/s output which carries 256 bits. If CSTo bit is set HIGH, the  
corresponding bit on CSTo output is transmitted in HIGH. If CSTo bit is LOW, the corresponding bit on the CSTo  
output is transmitted in LOW. The contents of the 256 CSTo bits of the CMH are transmitted sequentially on to the  
CSTo output pin and are synchronous to the ST-BUS streams. To allow for delay in any external control circuitry the  
contents of the CSTo bit is output one channel before the corresponding channel on the ST-BUS streams. For  
example, the contents of CSTo bit in position 0 (ST0, CH0) of the CMH, is transmitted synchronously with ST-BUS  
channel 31, bit 7. The contents of CSTo bit in position 32 (ST1, CH0) of the CMH is transmitted during ST-BUS  
channel 31 bit 6.  
Bit V/C (Variable/Constant Delay) on the Connect Memory High locations allow per-channel selection between  
Variable and Constant throughput delay capabilities.  
Initialization of the MT89L85  
On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially  
hazardous condition when multiple MT89L85 ST-BUS outputs are tied together to form matrices, as these outputs  
may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition.  
During the microprocessor initialization routine, the microprocessor should program the desired active paths  
through the matrices, and put all other channels into the high impedance state. Care should be taken that no two  
connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor  
controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMHb0s.  
7
Zarlink Semiconductor Inc.  

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