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MT89L85AP1 PDF预览

MT89L85AP1

更新时间: 2024-01-26 10:31:47
品牌 Logo 应用领域
美高森美 - MICROSEMI PC电信电信集成电路
页数 文件大小 规格书
25页 592K
描述
Digital Time Switch, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44

MT89L85AP1 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:NJESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.585 mm
湿度敏感等级:3功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.585 mmBase Number Matches:1

MT89L85AP1 数据手册

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MT89L85  
Data Sheet  
To summarize, any input time slot from input frame N will be always switched to the destination time slot on output  
frame N+2. In Constant Delay mode, the device throughput delay is calculated according to the following formula:  
DELAY = [32 + (32 - IN) + (OUT - 1)];  
(expressed in number of time slots)  
Where:  
IN is the number of the input time slot  
(from 1 to 32).  
OUT is the number of the output time slot  
(from 1 to 32).  
Microprocessor Port  
The MT89L85 microprocessor port has pin compatibility with Zarlink MT8985 Digital Switch devices providing a  
non-multiplexed bus architecture. The parallel port consists of an 8 bit parallel data bus (D0-D7), six address input  
lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control  
registers, Connection Memory High, Connection Memory Low and the Data Memory. All locations are read/written  
except for the data memory which can be read only.  
Accesses from the microport to the connection memory and the data memory are multiplexed with accesses from  
the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA).  
A5 A4 A3 A2 A1 A0  
LOCATION  
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Control Register  
Channel 0  
Channel 1  
1
1
1
1
1
Channel 31  
Figure 3 - Address Memory Map  
Note: "x" Don’t care.  
Software Control  
The address lines on the microprocessor interface give access to the MT89L85 internal registers and memories. If  
the A5,A1,A0 address line inputs are LOW, then the MT89L85 Internal Control Register is addressed (see Figure  
3). If A5 input line is HIGH, then the remaining address input lines are used to select Memory subsections of 32  
locations corresponding to the number of channels per input or output stream. As explained in the Control register  
description, the address input lines and the Stream Address bits (STA) of the Control register give the user the  
capability of selecting all positions of the MT89L85 Data and Connect memories.  
The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream  
Address bits (see Figure 4). The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory  
to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output  
ST-BUS streams. Bit 7 (Split Memory) of the Control register allows split memory operation whereby reads are  
from the Data memory and writes are to the Connect Memory LOW.  
The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the  
contents of the Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless  
6
Zarlink Semiconductor Inc.  

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