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MT8924 PDF预览

MT8924

更新时间: 2024-02-27 01:08:34
品牌 Logo 应用领域
MITEL PC
页数 文件大小 规格书
14页 136K
描述
PCM Conference Circuit (PCC) Preliminary Information

MT8924 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.4 mm
功能数量:1端子数量:24
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:2.65 mm
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:CONFERENCING CIRCUIT
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.4 mm
Base Number Matches:1

MT8924 数据手册

 浏览型号MT8924的Datasheet PDF文件第7页浏览型号MT8924的Datasheet PDF文件第8页浏览型号MT8924的Datasheet PDF文件第9页浏览型号MT8924的Datasheet PDF文件第11页浏览型号MT8924的Datasheet PDF文件第12页浏览型号MT8924的Datasheet PDF文件第13页 
MT8924  
Preliminary Information  
AC Electrical Characteristics - Clocked Timing* (TOP=0 to 70°C; VDD=5V±5%)  
Characteristics  
Clock period  
Sym  
Min  
Typ  
Max  
Units  
Test Conditions  
1
2
3
4
5
6
7
8
9
tCK  
230  
100  
100  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock low level width  
Clock high level width  
Clock rise time  
tWLCK  
tWHCK  
tRCK  
25  
25  
Clock fall time  
tFCK  
Sync. low setup time  
Sync. low level hold time  
Sync. high setup time  
Sync. high width  
tSLSY  
tHLSY  
tSHSY  
tWHSY  
tPDOS  
50  
40  
80  
tCK  
**  
10 OS propagation delay from rising  
edge of Clock  
100  
80  
C =50pF  
L
11 Cko propagation delay to Clock  
edges  
tPDEC  
ns  
C =50pF  
L
12 TD setup time  
13 TD hold time  
14 TD setup time  
15 TD hold time  
tSTD  
tHTD  
tSTF  
tHTD  
80  
40  
80  
40  
ns  
ns  
ns  
ns  
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up  
resistor. With Extra Bit Insert operating mode these times are 80ns longer.  
** With Extra Bit Insert operating mode this time becomes 3tCK  
.
t
RCK  
t
t
FCK  
CK  
Cki  
F0i  
t
t
WHCK  
WLCK  
t
HLSY  
t
SHSY  
t
SLSY  
t
WHSY  
t
HTD  
t
STD  
TD  
t
t
STF  
HTF  
TF  
t
PDEC  
t
PDEC  
Cko  
t
PDOS  
OS  
Figure 5 - Clock Timing  
8-12  

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