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MT8930CP PDF预览

MT8930CP

更新时间: 2024-01-20 17:55:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 网络接口数字传输接口电信集成电路电信电路综合业务数字网PC
页数 文件大小 规格书
41页 2518K
描述
Subscriber Network Interface Circuit

MT8930CP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.76
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.585 mm湿度敏感等级:1
功能数量:1端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:4.57 mm标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL SLIC温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:16.585 mm
Base Number Matches:1

MT8930CP 数据手册

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CMOS ST-BUS FAMILY MT8930C  
Subscriber Network Interface Circuit  
Data Sheet  
ISSUE 3  
November 1997  
Features  
ETS 300-012, CCITT I.430 and ANSI T1.605  
Ordering Information  
S/T interface  
MT8930CE  
MT8930CP  
28 Pin Plastic DIP  
44 Pin PLCC  
Full-duplex 2B+D, 192 kbit/s transmission  
Link activation/deactivation  
D-channel access contention resolution  
-40°C to +85°C  
Point-to-point, point-to-multipoint and star  
Description  
configurations  
Master (NT)/Slave (TE) modes of operation  
Exceeds loop length requirements  
Complete loopback testing capabilities  
On chip HDLC D-channel protocoller  
8 bit Motorola/Intel microprocessor interface  
The MT8930C Subscriber Network Interface Circuit  
(SNIC) implements the ETSI ETS 300-012, CCITT  
I.430 and ANSI T1.605 Recommendations for the  
ISDN S and T reference points. Providing point-to-  
point and point-to-multipoint digital transmission, the  
SNIC may be used at either end of the subscriber  
line (NT or TE).  
Controllerless or microprocessor-controlled  
operation  
Zarlink ST-BUS interface  
Low power CMOS technology  
Single 5 volt power supply  
An HDLC D-channel protocoller is included and  
controlled through a Motorola/Intel microprocessor  
port. A controllerless mode allows the SNIC to  
operate without a microprocessor.  
Applications  
The MT8930C is fabricated in Zarlink’s CMOS  
process.  
ISDN NT1  
ISDN S or T interface  
ISDN Terminal Adaptor (TA)  
Digital sets (TE1) - 4 wire ISDN interface  
Digital PABXs, Digital Line Cards (NT2)  
D-channel Priority  
Mechanism  
LTx  
DSTi  
ST-BUS  
S-Bus  
Link  
Interface  
DSTo  
VBias  
Interface  
LRx  
F0od  
C4b  
PLL  
HDLC  
Transceiver  
Timing  
and  
Link  
F0b  
STAR/Rsto  
CK/NT  
Activation  
Controller  
Control  
VDD  
Cmode  
VSS  
Microprocessor Interface  
Rsti  
HALF  
AD0-7  
R/W/WR,  
AFT/PRI  
DS/RD,  
DinB  
IRQ/NDA,  
DCack  
AS/ALE,  
P/SC  
CS,  
DReq  
Figure 1 - Functional Block Diagram  
1

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