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MT88L85AN PDF预览

MT88L85AN

更新时间: 2024-10-31 22:24:55
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
20页 354K
描述
3V Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface

MT88L85AN 数据手册

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MT88L85  
3V Integrated DTMF Transceiver  
with Power Down & Adaptive  
Advance Information  
Micro Interface  
ISSUE 1  
May 1995  
Features  
External power down pin  
Ordering Information  
MT88L85AE 24 Pin Plastic DIP  
Low voltage operation (2.7V - 3.6V)  
Central office quality DTMF transmitter/  
receiver  
MT88L85AN  
MT88L85AP  
24 Pin SSOP  
28 Pin PLCC  
Low power consumption  
-40°C to +85°C  
High speed adaptive micro interface  
Adjustable guard time  
The receiver section is based upon the industry  
standard MT8870 DTMF receiver while the  
Automatic tone burst mode  
Call progress tone detection to -30dBm  
transmitter utilizes  
a
switched capacitor D/A  
DTMF transmitter/receiver power down via  
register control  
converter for low distortion, high accuracy DTMF  
signalling. Internal counters provide a burst mode  
such that tone bursts can be transmitted with precise  
timing. A call progress filter can be selected allowing  
a microprocessor to analyze call progress tones.  
Applications  
Credit card systems  
Paging systems  
The MT88L85 utilizes an adaptive micro interface,  
which allows the device to be connected to a number  
of popular microcontrollers with minimal external  
logic. The MT88L85 provides enhanced power down  
Repeater systems/mobile radio  
Interconnect dialers  
Personal computers  
features.  
The transmitter and receiver may  
independently be powered down via register  
control. A full chip power down pin provides simple  
power and control capability.  
Description  
The MT88L85 is a monolithic DTMF transceiver with  
call progress filter.  
It is fabricated in CMOS  
technology offering low power consumption and high  
reliability.  
D0  
Data  
Row and  
D/A  
Transmit Data  
Bus  
D1  
D2  
D3  
Column  
TONE  
Converters  
Register  
Buffer  
Counters  
Status  
Register  
Interrupt  
Logic  
Tone Burst  
Gating Cct.  
Control  
Logic  
IRQ/CP  
Control  
Register  
A
IN+  
IN-  
GS  
+
-
Dial  
Tone  
Filter  
High Group  
Filter  
Digital  
DS/RD  
CS  
Algorithm  
and Code  
Converter  
Control  
Register  
B
I/O  
Low Group  
Filter  
Control  
OSC1  
OSC2  
Oscillator  
Circuit  
R/W/WR  
RS0  
Control  
Logic  
Receive Data  
Register  
Steering  
Logic  
Bias  
Circuit  
VDD VRef VSS  
ESt  
St/GT  
PWDN  
Figure 1 - Functional Block Diagram  
4-71  

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