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MT88L89ANR PDF预览

MT88L89ANR

更新时间: 2024-02-15 20:58:33
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
29页 649K
描述
Telecom IC

MT88L89ANR 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:SSOP针数:24
Reach Compliance Code:compliant风险等级:5.6
Base Number Matches:1

MT88L89ANR 数据手册

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MT88L89  
3 V Integrated DTMF Transceiver with  
Adaptive Micro Interface  
Data Sheet  
September 2005  
Features  
Complete DTMF transmitter/receiver  
Ordering Information  
Low voltage operation (2.7-3.6 V)  
MT88L89AE  
MT88L89AN  
MT88L89AP  
MT88L89AS  
20 Pin PDIP  
Tubes  
24 Pin SSOP Tubes  
Pin for pin compatible with existing MT8880,  
MT8888 and MT8889 devices  
28 Pin PLCC  
20 Pin SOIC  
Tubes  
Tubes  
MT88L89ANR1 24 Pin SSOP* Tubes  
Adaptive micro interface enables compatibility  
with Intel and Motorola processors  
MT88L89AS1  
MT88L89ANR 24 Pin SSOP Tape & Reel  
MT88L89ASR 20 Pin SOIC Tape & Reel  
20 Pin SOIC* Tubes  
DTMF transmitter/receiver power-down via  
register control  
MT88L89ASR1 20 Pin SOIC* Tape & Reel  
*Pb Free Matte Tin  
Adjustable guard time  
-40°C to +85°C  
Automatic tone burst mode  
Call progress tone detection to -30 dBm  
The receiver section is based upon the industry  
standard MT8870 DTMF receiver. The transmitter  
utilizes a switched capacitor D/A converter for low  
distortion, high accuracy DTMF signalling. Internal  
counters provide a burst mode such that tone bursts  
can be transmitted with precise timing. A call progress  
filter can be selected allowing a microprocessor to  
analyze call progress tones.  
Applications  
Credit card systems  
Paging systems  
Repeater systems/mobile radio  
Interconnect dialers  
Pay phones  
The MT88L89 utilizes an adaptive micro interface,  
which allows the device to be connected to a number  
of popular microcontrollers with minimal external logic.  
The MT88L89 provides enhanced power-down  
features. The transmitter and receiver may  
independently be powered down via register control.  
Remote monitor/Control systems  
Description  
The MT88L89 is a monolithic DTMF transceiver with  
call progress filter. It is fabricated in CMOS technology  
offering low power consumption and high reliability.  
D0  
Data  
Row and  
D/A  
Transmit Data  
Register  
Bus  
D1  
D2  
D3  
Column  
TONE  
Converters  
Buffer  
Counters  
Status  
Register  
Interrupt  
Logic  
Tone Burst  
Gating Cct.  
Control  
Logic  
IRQ/CP  
Control  
Register  
A
IN+  
IN-  
GS  
+
-
Dial  
Tone  
Filter  
High Group  
Filter  
Digital  
DS/RD  
CS  
Algorithm  
and Code  
Converter  
Control  
Register  
B
I/O  
Low Group  
Filter  
Control  
OSC1  
OSC2  
Oscillator  
R/W/WR  
RS0  
Circuit  
Control  
Logic  
Receive Data  
Register  
Steering  
Logic  
Bias  
Circuit  
VDD VRef VSS  
ESt  
St/GT  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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