Datasheet > MT58L256L18P1F-5

MT58L256L18P1F-5

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	466K
描述
Cache SRAM, 256KX18, 2.8ns, CMOS, PBGA165, FBGA-165

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MT58L256L18P1F-5 数据手册

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

GENERALDESCRIPTION(continued)

(CE#), two additional chip enables for easy depth ex-

pansion (CE2, CE2#), burst control inputs (ADSC#,

ADSP#, ADV#), byte write enables (BWx#) and global

write (GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is

also a burst mode input (MODE) that selects between

interleaved and linear burst modes. The data-out (Q),

enabled by OE#, is also asynchronous. WRITE cycles

can be from one to two bytes wide (x18) or from one to

four bytes wide (x32/x36), as controlled by the write

control inputs.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) inputs. Subsequent burst addresses can be

internally generated as controlled by the burst advance

input (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls DQb

pins and DQPb. During WRITE cycles on the x32 and

x36 devices, BWa# controls DQa pins and DQPa; BWb#

controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. GW#

LOW causes all bytes to be written. Parity bits are only

available on the x18 and x36 versions.

This device incorporates a single-cycle deselect fea-

ture during READ cycles. If the device is immediately

deselected after a READ cycle, the output bus goes to a

High-Z state KQHZ nanoseconds after the rising edge

of clock.

Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V

V^DDpower supply, and all inputs and outputs are TTL-

compatible. Users can choose either a 3.3V or 2.5V I/O

version. The device is ideally suited for Pentium and

PowerPC pipelined systems and systems that benefit

from a very wide, high-speed data bus. The device is

also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-

wide applications.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

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