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MT58L256L32DF-10IT PDF预览

MT58L256L32DF-10IT

更新时间: 2023-01-02 19:58:40
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
26页 419K
描述
Standard SRAM, 256KX32, 5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

MT58L256L32DF-10IT 数据手册

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8Mb: 512K x 18, 256K x 32/36  
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM  
MT58L512L18D, MT58L256L32D,  
8Mb SYNCBURST  
SRAM  
MT58L256L36D  
3.3V VDD, 3.3V I/O, Pipelined, Double-  
Cycle Deselect  
FEATURES  
• Fast clock and OE# access times  
100-Pin TQFP**  
• Single +3.3V +0.3V/-0.165V power supply (VDD)  
• Separate +3.3V isolated output buffer supply (VDDQ)  
• SNOOZE MODE for reduced-power standby  
• Common data inputs and data outputs  
• Individual BYTE WRITE control and GLOBAL WRITE  
• Three chip enables for simple depth expansion and  
address pipelining  
• Clock-controlled and registered addresses, data I/Os  
and control signals  
• Internally self-timed WRITE cycle  
• Burst control (interleaved or linear burst)  
• Automatic power-down for portable applications  
• 100-pin TQFP package  
165-Pin FBGA  
• 165-pin FBGA package  
• Low capacitive bus loading  
• x18, x32, and x36 versions available  
OPTIONS  
MARKING  
• Timing (Access/Cycle/MHz)  
3.5ns/6ns/166 MHz  
4.0ns/7.5ns/133 MHz  
5ns/10ns/100 MHz  
-6  
-7.5  
-10  
• Configurations  
512K x 18  
MT58L512L18D  
MT58L256L32D  
MT58L256L36D  
256K x 32  
256K x 36  
NOTE:1. JEDEC-standard MS-026 BHA (LQFP).  
• Packages  
100-pin TQFP (2-chip enable)  
100-pin TQFP (3-chip enable)  
165-pin, 13mm x 15mm FBGA  
T
S
F*  
GENERAL DESCRIPTION  
TheMicron® SyncBurstSRAMfamilyemployshigh-  
speed, low-power CMOS designs that are fabricated us-  
ing an advanced CMOS process.  
• Operating Temperature Range  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)**  
None  
IT  
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18,  
256K x 32, or 256K x 36 SRAM core with advanced syn-  
chronous peripheral circuitry and a 2-bit burst counter.  
All synchronous inputs pass through registers controlled  
by a positive-edge-triggered single-clock input (CLK).  
The synchronous inputs include all addresses, all data  
inputs, active LOW chip enable (CE#), two additional  
chip enables for easy depth expansion (CE2, CE2#), burst  
control inputs (ADSC#, ADSP#, ADV#), byte write  
enables (BWx#) and global write (GW#). Note that CE2#  
is not available on the T Version.  
Part Number Example  
MT58L512L18DT-7.5  
* A Part Marking Guide for the FBGA devices can be found on Micron’s  
Web site—http://www.micron.com/support/index.html.  
** Industrial temperature range offered in specific speed grades and  
configurations. Contact factory for more information.  
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM  
MT58L512L18D_D.p65 – Rev. 2/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2002, Micron Technology, Inc.  
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