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Datasheet > MT58L128L36P1T-7.5
MT58L128L36P1T-7.5 PDF预览

MT58L128L36P1T-7.5

更新时间： 2024-02-23 17:12:52
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
30页 466K
描述
Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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MT58L128L36P1T-7.5 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.53
最长访问时间：4 nsJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：4718592 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

MT58L128L36P1T-7.5 数据手册

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4Mb: 256K x 18, 128K x 32/36  
PIPELINED, SCD SYNCBURST SRAM  
TQFPPINDESCRIPTIONS(continued)  
x18  
x32/x36  
SYMBOL TYPE  
DESCRIPTION  
85  
85  
ADSC#  
Input Synchronous Address Status Controller: This active LOW input  
interrupts any ongoing burst, causing a new external address to  
be registered. A READ or WRITE is performed using the new  
address if CE# is LOW. ADSC# is also used to place the chip into  
power-down state when CE# is HIGH.  
31  
64  
31  
64  
MODE  
ZZ  
Input Mode: This input selects the burst sequence. A LOW on this pin  
selects “linear burst.” NC or HIGH on this pin selects “interleaved  
burst.” Do not alter input state while device is operating.  
Input Snooze Enable: This active HIGH, asynchronous input causes the  
device to enter a low-power standby mode in which all data in  
the memory array is retained. When ZZ is active, all other inputs  
are ignored.  
(a) 58, 59,  
62, 63, 68, 69, 56–59, 62, 63  
72, 73  
(b) 8, 9, 12,  
13, 18, 19, 22, 72–75, 78, 79  
(a) 52, 53,  
DQa  
DQb  
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte  
Output “b” is DQb pins. For the x32 and x36 versions, Byte “a” is DQa  
pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is  
DQd pins. Input data must meet setup and hold times around  
the rising edge of CLK.  
(b) 68, 69  
23  
(c) 2, 3, 6-9,  
12, 13  
(d) 18, 19,  
22–25, 28, 29  
DQc  
DQd  
74  
24  
–
51  
80  
1
NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these pins are  
NC/DQPb  
NC/DQPc  
NC/DQPd  
I/O  
No Connect (NC). On the x18 version, Byte “a” parity is DQPa;  
Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is  
DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d”  
parity is DQPd.  
–
30  
14, 15, 41, 65, 14, 15, 41, 65,  
91 91  
VDD  
VDDQ  
VSS  
Supply Power Supply: See DC Electrical Characteristics and Operating  
Conditions for range.  
4, 11, 20, 27, 4, 11, 20, 27,  
54, 61, 70, 77 54, 61, 70, 77  
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics  
and Operating Conditions for range.  
5, 10, 17, 21, 5, 10, 17, 21,  
26, 40, 55, 60, 26, 40, 55, 60,  
67, 71, 76, 90 67, 71, 76, 90  
Supply Ground: GND.  
38, 39  
38, 39  
DNU  
NC  
–
–
Do Not Use: These signals may either be unconnected or wired to  
GND to improve package heat dissipation.  
1–3, 6, 7, 16,  
25, 28–30,  
51–53, 56, 57,  
66, 75, 78, 79,  
95, 96  
16, 66  
No Connect: These signals are not internally connected and  
may be connected to ground to improve package heat  
dissipation.  
42, 43  
42, 43  
NF  
–
No Function: These pins are internally connected to the die and  
have the capacitance of input pins. It is allowable to leave these  
pins unconnected or driven by signals. Reserved for address  
expansion; pin 43 becomes an SA at 8Mb density and pin 42  
becomes an SA at 16Mb density.  
4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM  
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
7
©2003,MicronTechnology,Inc.  
1...45678910...30

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