Datasheet > MT58L128L36P1T-6

MT58L128L36P1T-6

更新时间： 2024-02-15 22:38:41

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
30页	466K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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MT58L128L36P1T-6 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.56
最长访问时间：	3.5 ns	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	4718592 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
功能数量：	1	端子数量：	100
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	128KX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

MT58L128L36P1T-6 数据手册

4Mb: 256K x 18, 128K x 32/36

PIPELINED, SCD SYNCBURST SRAM

GENERALDESCRIPTION(continued)

(CE#), two additional chip enables for easy depth ex-

pansion (CE2, CE2#), burst control inputs (ADSC#,

ADSP#, ADV#), byte write enables (BWx#) and global

write (GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is

also a burst mode input (MODE) that selects between

interleaved and linear burst modes. The data-out (Q),

enabled by OE#, is also asynchronous. WRITE cycles

can be from one to two bytes wide (x18) or from one to

four bytes wide (x32/x36), as controlled by the write

control inputs.

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) inputs. Subsequent burst addresses can be

internally generated as controlled by the burst advance

input (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls DQb

pins and DQPb. During WRITE cycles on the x32 and

x36 devices, BWa# controls DQa pins and DQPa; BWb#

controls DQb pins and DQPb; BWc# controls DQc pins

and DQPc; BWd# controls DQd pins and DQPd. GW#

LOW causes all bytes to be written. Parity bits are only

available on the x18 and x36 versions.

This device incorporates a single-cycle deselect fea-

ture during READ cycles. If the device is immediately

deselected after a READ cycle, the output bus goes to a

High-Z state KQHZ nanoseconds after the rising edge

of clock.

Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V

V^DDpower supply, and all inputs and outputs are TTL-

compatible. Users can choose either a 3.3V or 2.5V I/O

version. The device is ideally suited for Pentium and

PowerPC pipelined systems and systems that benefit

from a very wide, high-speed data bus. The device is

also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-

wide applications.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM

MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

1 234 5 6 7...30

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与MT58L128L36P1T-6相关器件

型号	品牌	描述	获取价格	数据表
MT58L128L36P1T-6IT	CYPRESS	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
MT58L128L36P1T-7.5	CYPRESS	Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100	获取价格
MT58L128L36P1T-7.5IT	CYPRESS	Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
MT58L128V18F	MICRON	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM	获取价格
MT58L128V18FF-10	CYPRESS	Standard SRAM, 128KX18, 10ns, CMOS, PBGA165, FBGA-165	获取价格
MT58L128V18FF-6.8	CYPRESS	Standard SRAM, 128KX18, 6.8ns, CMOS, PBGA165, FBGA-165	获取价格

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