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Datasheet > MT58L128L36P1T-4.4
MT58L128L36P1T-4.4 PDF预览

MT58L128L36P1T-4.4

更新时间： 2024-01-09 09:41:44
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
30页 466K
描述
Cache SRAM, 128KX36, 2.6ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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MT58L128L36P1T-4.4 技术参数

是否Rohs认证：不符合生命周期：Transferred
零件包装代码：QFP包装说明：PLASTIC, MS-026, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.53
Is Samacsys：N最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：225 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.575 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

MT58L128L36P1T-4.4 数据手册

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4Mb: 256K x 18, 128K x 32/36  
PIPELINED, SCD SYNCBURST SRAM  
TQFPPINDESCRIPTIONS  
x18  
x32/x36  
SYMBOL TYPE  
DESCRIPTION  
37  
36  
37  
36  
SA0  
SA1  
SA  
Input Synchronous Address Inputs: These inputs are registered and  
must meet the setup and hold times around the rising edge of  
CLK.  
32–35, 44–50, 32–35, 44–50,  
80–82, 99,  
100  
81, 82, 99,  
100  
93  
94  
–
93  
94  
95  
96  
BWa#  
BWb#  
BWc#  
BWd#  
Input Synchronous Byte Write Enables: These active LOW inputs allow  
individual bytes to be written and must meet the setup and hold  
times around the rising edge of CLK. A byte write enable is LOW  
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,  
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and  
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and  
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins  
and DQPc; BWd# controls DQd pins and DQPd. Parity is only  
available on the x18 and x36 versions.  
–
87  
88  
89  
87  
88  
89  
BWE#  
GW#  
CLK  
Input Byte Write Enable: This active LOW input permits BYTE WRITE  
operations and must meet the setup and hold times around the  
rising edge of CLK.  
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit  
WRITE to occur independent of the BWE# and BWx# lines and must  
meet the setup and hold times around the rising edge of CLK.  
Input Clock: This signal registers the address, data, chip enable, byte write  
enables and burst control inputs on its rising edge. All synchronous  
inputs must meet setup and hold times around the clock’s rising  
edge.  
98  
92  
97  
98  
92  
97  
CE#  
CE2#  
CE2  
Input Synchronous Chip Enable: This active LOW input is used to enable  
the device and conditions the internal use of ADSP#. CE# is sampled  
only when a new external address is loaded.  
Input Synchronous Chip Enable: This active LOW input is used to enable  
the device and is sampled only when a new external address is  
loaded.  
Input Synchronous Chip Enable: This active HIGH input is used to enable  
the device and is sampled only when a new external address is  
loaded.  
86  
83  
86  
83  
OE#  
Input Output Enable: This active LOW, asynchronous input enables the  
data I/O output drivers.  
ADV#  
Input Synchronous Address Advance: This active LOW input is used to  
advance the internal burst counter, controlling burst access after the  
external address is loaded. A HIGH on this pin effectively causes wait  
states to be generated (no address advance). To ensure use of correct  
address during a WRITE cycle, ADV# must be HIGH at the rising edge  
of the first clock after an ADSP# cycle is initiated.  
84  
84  
ADSP#  
Input Synchronous Address Status Processor: This active LOW input  
interrupts any ongoing burst, causing a new external address to be  
registered. A READ is performed using the new address,  
independent of the byte write enables and ADSC#, but dependent  
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-  
down state is entered if CE2 is LOW or CE2# is HIGH.  
(continued on next page)  
4Mb:256Kx18, 128Kx32/36Pipelined, SCDSyncBurstSRAM  
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
6
©2003,MicronTechnology,Inc.  
1...3456789...30

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