Datasheet > MT58L128L36F1T-7.5IT

MT58L128L36F1T-7.5IT

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	628K
描述
Cache SRAM, 128KX36, 7.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

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PRELIMINARY

4Mb: 256K x 18, 128K x 32/36

FLOW-THROUGH SYNCBURST SRAM

FBGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

ADSP#

Input Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

ADSC#

Input Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

MODE

(LB0#)

Input Mode: This input selects the burst sequence. A LOW on this input

selects “linear burst.” NC or HIGH on this input selects “interleaved

burst.” Do not alter input state while device is operating.

(a) 10J, 10K, (a) 10J, 10K,

10L, 10M, 11D, 10L, 10M, 11J,

11E, 11F, 11G 11K, 11L, 11M

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;

Output Byte “b” is associated with DQbs. For the x32 and x36 versions,

Byte “a” is associated with DQas; Byte “b” is associated with DQbs;

Byte “c” is associated with DQcs; Byte “d” is associated with DQds.

Input data must meet setup and hold times around the rising edge

of CLK.

(b) 1J, 1K,

(b) 10D, 10E,

1L, 1M, 2D, 10F, 10G, 11D,

2E, 2F, 2G

11E, 11F, 11G

1F, 1G, 2D,

2E, 2F, 2G

(d) 1J, 1K, 1L,

1M, 2J, 2K,

2L, 2M

11C

–

11N

11C

NC/DQPa

NC/DQPb

NC/DQPc

NC/DQPd

NC/

I/O

No Connect/Parity Data I/Os: On the x32 version, these are No

Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”

parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

–

4D, 4E, 4F,

4G, 4H, 4J,

4K, 4L, 4M,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

4D, 4E, 4F,

4G, 4H, 4J,

4K, 4L, 4M,

8D, 8E, 8F,

8G, 8H, 8J,

8K, 8L, 8M

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

3C, 3D, 3E,

3F, 3G, 3J,

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

3C, 3D, 3E,

3F, 3G, 3J,

3K, 3L, 3M,

3N, 9C, 9D,

9E, 9F, 9G,

9J, 9K, 9L,

9M, 9N

DDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

Operating Conditions for range.

(continued on next page)

4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM

MT58L256L18F1_C.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

1...6 7 8910 11 12...31

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与MT58L128L36F1T-7.5IT相关器件

型号	品牌	描述	获取价格	数据表
MT58L128L36P1B-10	CYPRESS	Standard SRAM, 128KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119	获取价格
MT58L128L36P1B-5	CYPRESS	Standard SRAM, 128KX36, 2.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119	获取价格
MT58L128L36P1B-6	CYPRESS	Standard SRAM, 128KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028BHA, BGA-119	获取价格
MT58L128L36P1F-10	CYPRESS	Cache SRAM, 128KX36, 5ns, CMOS, PBGA165, FBGA-165	获取价格
MT58L128L36P1F-4	CYPRESS	Standard SRAM, 128KX36, 2.3ns, CMOS, PBGA165, FBGA-165	获取价格
MT58L128L36P1F-4.4	CYPRESS	Cache SRAM, 128KX36, 2.6ns, CMOS, PBGA165, FBGA-165	获取价格

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