256K x 36
2.5V VDD, HSTL, PIPELINED DDR SRAM
MT57V256H36P
9Mb
DDR SRAM
FEATURES
• Fast cycle times: 5ns and 6ns
165-Ball FBGA
• 256K x 36 configuration
• Pipelined double data rate operation
• Single +2.5V ±0.1V power supply (VDD)
• Separate isolated output buffer supply (VDDQ)
• JEDEC-standard HSTL I/O
• User-selectable trip point with VREF
• HSTL programmable impedance outputs synchro-
nized to optional dual data clocks
• Echo clock outputs
• JTAG boundary scan
• Fully static design for reduced-power standby
• Clock-stop capability
• Common data inputs and data outputs
• Low control ball count
• Internally self-timed, registered LATE WRITE cycle
• Linear burst order with four-tick burst counter
• 13 x 15mm, 1mm pitch, 11 x 15 grid FBGA package
• Full data coherency, providing most current data
OPTIONS
MARKING*
latched on the rising edge of K and K#. The synchronous
inputs include all addresses, all data inputs, active LOW
load (LD#) and read/write (R/W#). Write data is regis-
tered on the rising edges of both K and K#. Read data is
driven on the rising edge of C and C# if provided, or on the
rising edge of K and K# if C and C# are not provided.
Asynchronousinputsincludeimpedancematch(ZQ).
Synchronous data outputs (Q) are closely matched to the
two echo clocks (CQ and CQ#), which can be used as data
receive clocks. Output data clocks (C, C#) are also pro-
vided for maximum system clocking and data synchroni-
zation flexibility.
Additionalwriteregistersareincorporatedtoenhance
pipelinedWRITEcyclesandreduceREAD-to-WRITEturn-
around time. WRITE cycles are self-timed.
Thedevicedoesnotutilizeinternalphase-lockedloops
and can therefore be placed into a stopped-clock state to
minimize power without lengthy restart times.
• Clock Cycle Timing
5ns (200 MHz)
6ns (167 MHz)
-5
-6
• Configuration
256K x 36
MT57V256H36P
F
• Package
165-ball, 13mm x 15mm FBGA
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/numberguide.
VALID PART NUMBERS
PART NUMBER
MT57V256H36PF-xx
DESCRIPTION
256K x 36, HSTL, DDR, Pipelined
GENERAL DESCRIPTION
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK) and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs use
JEDEC-standard 2.5V I/O levels to shift data during this
testing mode of operation.
TheMicron®DDRSynchronousSRAMemployshigh-
speed, low-power CMOS designs using an advanced 6T
CMOS process.
The DDR SRAM integrates a 9Mb SRAM core with
advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through reg-
isters controlled by an input clock pair (K and K#) and are
The device can be used in HSTL systems by supplying
an appropriate reference voltage (VREF). The device is
256K x 36 2.5V VDD, HSTL, Pipelined DDR SRAM
MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02
©2002, Micron Technology, Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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