Datasheet > MT57W1MH18BF-5

MT57W1MH18BF-5

更新时间： 2023-01-02 15:20:50

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器
页数	文件大小	规格书
27页	400K
描述
DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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MT57W1MH18BF-5 数据手册

2 MEG X 8, 1 MEG X 18, 512K X 36

1.8V VDD, HSTL, DDRIIb2 SRAM

MT57W2MH8B

MT57W1MH18B

MT57W512H36B

18Mb DDRII CIO SRAM

2-Word Burst

Features

•

DLL circuitry for accurate output data placement

Pipelined, double-data rate operation

Common data input/output bus

Figure 1: 165-Ball FBGA

Fast clock to valid data times

Full data coherency, providing most current data

Two-tick burst counter for low DDR transaction size

Two input clocks (K and K#) for precise DDR timing at

clock rising edges only

•

Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

•

Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

•

Permits up to one new data request per clock cycle

Simple control logic for easy depth expansion

Internally self-timed, registered writes

Core VDD = 1.8V (±±.1V); I/O VDDQ = 1.5V to VDD

(±±.1V) HSTL

Table 1:

Valid Part Numbers

•

Clock-stop capability withꢀµsꢀrestart

13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA package

User-programmable impedance output

JTAG boundary scan

PART NUMBER

DESCRIPTION

MT57W2MH8BF-xx

MT57W1MH18BF-xx

MT57W512H36BF-xx

2 Meg x 8, DDRIIb2 FBGA

1 Meg x 18, DDRIIb2 FBGA

512K x 36, DDRIIb2 FBGA

Options

Marking¹

General Description

The Micron^®DDRII synchronous, pipelined burst

SRAM employs high-speed, low-power CMOS designs

using an advanced 6T CMOS process.

•

Clock Cycle Timing

-3

-3.3

-4

3ns (333 MHz)

3.3ns (3±± MHz)

4ns (25± MHz)

The DDR SRAM integrates an SRAM core with

advanced synchronous peripheral circuitry and a burst

counter. All synchronous inputs pass through registers

controlled by an input clock pair (K and K#) and are

latched on the rising edge of K and K#. The synchro-

nous inputs include all addresses, all data inputs,

active LOW load (LD#), read/write (R/W#), and active

LOW byte writes or nibble writes (BWx# or NWx#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K# if C

and C# are not provided.

5ns (2±± MHz)

6ns (167 MHz)

7.5ns (133 MHz)

Configurations

2 Meg x 8

1 Meg x 18

512K x 36

Package

-5

-6

-7.5

•

MT57W2MH8B

MT57W1MH18B

MT57W512H36B

•

165-ball, 13mm x 15mm FBGA

Operating Temperature Range

Commercial (±°C ? T_A? +7±°C)

None

NOTE:

Asynchronous inputs include impedance match

(ZQ). Synchronous data outputs (Q, sharing the same

physical balls as the data inputs D) are tightly matched

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

18Mb: 1.8V VDD, HSTL, DDRIIb2 SRAM

MT57W1MH18B_H.fm – Rev. H, Pub. 3/03

12 3 4 5 6 7...27

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与MT57W1MH18BF-5相关器件

型号	品牌	描述	获取价格	数据表
MT57W1MH18BF-6	ROCHESTER	1MX18 DDR SRAM, 0.5ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57W1MH18BF-7.5	ROCHESTER	1MX18 DDR SRAM, 0.5ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57W1MH18CF-3	CYPRESS	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57W1MH18CF-3.3	CYPRESS	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57W1MH18CF-4	CYPRESS	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57W1MH18CF-4	ROCHESTER	1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格

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