2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDR SIO SRAM
MT57W2MH8C
MT57W1MH18C
MT57W512H36C
18Mb DDR SIO SRAM
2-WORD BURST
Features
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DLL circuitry for accurate output data placement
Separate independent read and write data ports
DDR READ or WRITE operation initiated each cycle
Fast clock to valid data times
Full data coherency, providing most current data
Two-tick burst counter for low DDR transaction size
Double data rate operation on read and write ports
Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
Single address bus
Simple control logic for easy depth expansion
Internally self-timed, registered writes
Core VDD = 1.8V (±±.1V); I/O VDDQ = 1.5V to VDD
(±±.1V) HSTL
Clock-stop capability withꢀµs restart
13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA
package
User-programmable impedance output
JTAG boundary scan
Figure 1: 165-Ball FBGA
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Table 1:
Valid Part Numbers
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PART NUMBER
DESCRIPTION
MT57W2MH8CF-xx
MT57W1MH18CF-xx
MT57W512H36CF-xx
2 Meg x 8, DDR SIOb2 FBGA
1 Meg x 18, DDR SIOb2 FBGA
512K x 36, DDR SIOb2 FBGA
Options
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Marking1
Clock Cycle Timing
3ns (333 MHz)
3.3ns (3±± MHz)
4ns (25± MHz)
-3
-3.3
-4
General Description
The Micron® DDR separate I/O, synchronous, pipe-
lined burst SRAM employs high-speed, low-power
CMOS designs using an advanced 6T CMOS process.
The DDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on the rising edge of the K input clock. Each address
location is associated with two words that burst
sequentially into or out of the device. Bus turnaround
cycles are eliminated and a new data transaction can
be requested each clock cycle, permitting higher
request rates than DDR SRAMs without separated
input and output buses.
5ns (2±± MHz)
6ns (167 MHz)
7.5ns (133 MHz)
Configurations
2 Meg x 8
1 Meg x 18
512K x 36
Package
-5
-6
-7.5
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MT57W2MH8C
MT57W1MH18C
MT57W512H36C
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165-ball, 13mm x 15mm FBGA
Operating Temperature Range
Commercial (±°C ?ꢀTA ? +7±°C)
F
None
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
18Mb: 2 Meg x 8, 1 Meg x 18, 512K x 36, 1.8V VDD, HSTL, DDR SIO SRAM
MT57W1MH18C_H.fm – Rev. H, Pub. 3/03
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©2003 Micron Technology, Inc.