16Mb : 1 MEG x16
EDO DRAM
MT4C1M16E5 – 1 Me g x 16, 5V
MT4LC1M16E5 – 1 Me g x 16, 3.3V
EDO DRAM
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/datasheets/sdramds.html
FEATURES
• JEDEC- and industry-standard x16 tim ing,
functions, pinouts, and packages
PIN ASSIGNMENT(To p Vie w )
• High-perform ance CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±10%)
• All inputs, outputs and clocks are TTL-com patible
• Refresh m odes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional self refresh (S)
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 colum n addresses)
• Extended Data-Out (EDO) PAGE MODE access
• 5V-tolerant inputs and I/ Os on 3.3V devices
44/50-Pin TSOP
42-Pin SOJ
VCC
DQ0
DQ1
DQ2
DQ3
VCC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
V
CC
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
VSS
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
2
DQ15
DQ14
DQ13
DQ12
VSS
3
4
5
VCC
VSS
6
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
DQ4
DQ5
DQ6
DQ7
NC
7
DQ11
DQ10
DQ9
DQ8
NC
9
10
11
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NC
CASL#
CASH#
OE#
A9
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
WE#
RAS#
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
OPTIONS
• Voltages1
3.3V
MARKING
NC
A8
A0
A7
LC
C
A1
A6
A2
A5
5V
A3
VCC
A3
A4
VCC
VSS
• Refresh Addressing
1,024 (1K) rows
NOTE: The " #" symbol indicates signal is active LOW.
E5
• Packages
Plastic SOJ (400 m il)
Plastic TSOP (400 m il)
D J
TG
1 MEG x 16 EDO DRAM PART NUMBERS
• Tim in g
PARTNUMBER
Vcc REFRESH PACKAGE REFRESH
50ns access
60ns access
-5
-6
MT4LC1M16E5DJ-x
MT4LC1M16E5DJ-xS
MT4LC1M16E5TG-x
MT4LC1M16E5TG-xS
MT4C1M16E5DJ-x
MT4C1M16E5TG-x
3.3V
3.3V
3.3V
3.3V
5V
1K
1K
1K
1K
1K
1K
400-SOJ Standard
400-SOJ Self
400-TSOP Standard
400-TSOP Self
• Refresh Rates
Standard Refresh (16m s period)
Self Refresh (128m s period)
Non e
S2
400-SOJ Standard
400-TSOP Standard
5V
• Operating Tem perature Range
Com m ercial (0oC to +70oC)
Extended (-20oC to +80oC)
Non e
ET
NOTE: “-x” indicates speed grade marking under timing
options.
Part Number Example:
GENERAL DESCRIPTION
MT4LC1M16E5TG-6
The 1 Meg x 16 is a random ly accessed, solid-state
m em ory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
The CAS# function and tim ing are determ ined by
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one
NOTE: 1. The third field distinguishes the low voltage offering: LC desig-
nates Vcc = 3.3V and C designates Vcc = 5V.
2. Available only on MT4LC1M16E5 (3.3V)
KEY TIMING PARAMETERS
t
t
t
t
t
t
SPEED
-5
RC
RAC
PC
AA
CAC
CAS
84ns
50ns
60ns
20ns
25ns
25ns
30ns
15ns
17ns
8ns
-6
104ns
10ns
1 Meg x 16 EDO DRAM
1
D52_B.p65 –Rev. B;Pub. 3/01
©2001, Micron Technology, Inc
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.