Datasheet > MT4LC4M4E8DJ

MT4LC4M4E8DJ

更新时间： 2024-02-15 21:40:54

品牌	Logo	应用领域
镁光 - MICRON		动态存储器
页数	文件大小	规格书
23页	291K
描述
4 MEG x 4 EDO DRAM

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中文翻译

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数据手册

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MT4LC4M4E8DJ 数据手册

4 MEG x 4

EDO DRAM

TECHNOLOGY, INC.

MT4LC4M4E8, MT4C4M4E8

MT4LC4M4E9, MT4C4M4E9

DRAM

FEATURES

• Industry-standard x4 pinout, timing, functions and

packages

• State-of-the-art, high-performance, low-power CMOS

silicon-gate process

PIN ASSIGNMENT (Top View)

24/26-Pin SOJ

24/26-Pin TSOP

(DA-2)

(DB-2)

• Single power supply (+3.3V ±0.3V or +5V ±10%)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-

BEFORE-RAS# (CBR)

• Optional Self Refresh (S) for low-power data retention

• 11 row, 11 column addresses (2K refresh) or

12 row, 10 column addresses (4K refresh)

• Extended Data-Out (EDO) PAGE MODE access cycle

• 5V-tolerant inputs and I/ Os on 3.3V devices

DQ1

DQ2

WE#

RAS#

DQ1

DQ2

WE#

RAS#

VSS

DQ4

DQ3

CAS#

OE#

DQ4

DQ3

CAS#

OE#

*NC/A11

A10

VSS

OPTIONS

MARKING

* NC on 2K refresh and A11 on 4K refresh options.

• Voltages

3.3V

Note: The “#” symbol indicates signal is active LOW.

4 MEG x 4 EDO DRAM PART NUMBERS

• Refresh Addressing

2,048 (i.e. 2K) Rows

4,096 (i.e. 4K) Rows

PART NUMBER

Vcc

3.3V

REFRESH PACKAGE REFRESH

MT4LC4M4E8DJ

MT4LC4M4E8DJS

MT4LC4M4E8TG

MT4LC4M4E8TGS

MT4LC4M4E9DJ

MT4LC4M4E9DJS

MT4LC4M4E9TG

MT4LC4M4E9TGS

MT4C4M4E8DJ

MT4C4M4E8DJS

MT4C4M4E8TG

MT4C4M4E8TGS

MT4C4M4E9DJ

MT4C4M4E9DJS

MT4C4M4E9TG

MT4C4M4E9TGS

SOJ

Standard

Self

• Packages

Plastic SOJ (300 mil)

Plastic TSOP (300 mil)

TSOP

SOJ

Standard

Self

• Timing

Standard

Self

50ns access

60ns access

-5

-6

SOJ

TSOP

SOJ

Standard

Self

• Refresh Rates

Standard Refresh

Self Refresh (128ms period)

None

Standard

Self

SOJ

TSOP

SOJ

Standard

Self

• Part Number Example: MT4LC4M4E8DJ-6

Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in

two places - MT4LC4M4E8. The third field distinguishes the low voltage

offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field

distinguishes various options: E8 designates a 2K refresh and E9 designates a

4K refresh for EDO DRAMs.

Standard

Self

SOJ

TSOP

Standard

Self

KEY TIMING PARAMETERS

GENERAL DESCRIPTION

SPEED

-5

RAC

CAC

CAS

The 4 Meg x 4 DRAM is a randomly accessed, solid-state

memory containing 16,777,216 bits organized in a x4 con-

figuration. RAS# is used to latch the row address (first 11

bits for 2K and first 12 bits for 4K). Once the page has been

opened by RAS#, CAS#is used to latch the column address

84ns

50ns

60ns

20ns

25ns

30ns

13ns

15ns

8ns

-6

104ns

10ns

4 Meg x 4 EDO DRAM

D47.pm5 – Rev. 3/97

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1997, Micron Technology, Inc.

12 3 4 5 6 7...23

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与MT4LC4M4E8DJ相关器件

型号	品牌	获取价格	描述	数据表
MT4LC4M4E8DJS	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E8TG	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E8TGS	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E9	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E9DJ	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E9DJS	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E9TG	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC4M4E9TGS	MICRON	获取价格	4 MEG x 4 EDO DRAM
MT4LC8M8B6DJ-5	MICRON	获取价格	DRAM
MT4LC8M8B6DJ-5S	MICRON	获取价格	DRAM

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