8 MEG x 8
FPM DRAM
MT4LC8M8E1, MT4LC8M8B6
DRAM
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/datasheets/dramds.html
FEATURES
PIN ASSIGNMENT (To p Vie w )
• Single +3.3V ±±.3V ꢀpoeꢁ ꢂsꢀꢀlꢃ
• Indsꢂtꢁꢃ-ꢂtandaꢁd x8 ꢀinpst, timing, fsnctipnꢂ,
and ꢀackageꢂ
32-Pin TSOP
32-Pin SOJ
• 13 ꢁpo, 1± cplsmn addꢁeꢂꢂeꢂ (E1) pꢁ
12 ꢁpo, 11 cplsmn addꢁeꢂꢂeꢂ (B6)
• High-ꢀeꢁfpꢁmance CMOS ꢂilicpn-gate ꢀꢁpceꢂꢂ
• All inꢀstꢂ, pstꢀstꢂ and clpckꢂ aꢁe LVTTL-
cpmꢀatible
• FAST PAGE MODE (FPM) acceꢂꢂ
• 4,±96-cꢃcle CAS#-BEFORE-RAS# (CBR) REFRESH
diꢂtꢁibsted acꢁpꢂꢂ 64mꢂ
V
CC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
V
CC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
DQ0
DQ1
DQ2
DQ3
NC
DQ7
DQ6
DQ5
DQ4
DQ0
DQ1
DQ2
DQ3
NC
DQ7
DQ6
DQ5
DQ4
Vss
CAS#
OE#
NC/A12**
A11
A10
A9
VSS
V
CC
CAS#
OE#
NC/A12**
A11
A10
A9
A8
A7
A6
VSS
VCC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
9
WE#
RAS#
A0
A1
A2
A3
A4
A5
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
• Oꢀtipnal ꢂelf ꢁefꢁeꢂh (S) fpꢁ lpo-ꢀpoeꢁ data
ꢁetentipn
A8
A7
A6
VSS
CC
OPTIONS
MARKING
VCC
• Refꢁeꢂh Addꢁeꢂꢂing
4,±96 (4K) ꢁpoꢂ
8,192 (8K) ꢁpoꢂ
B6
E1
**A12 on E1 version, NC on B6 version
• Plaꢂtic Packageꢂ
8 MEG x 8 FPM DRAM PART NUMBERS
32-ꢀin SOJ (4±± mil)
32-ꢀin TSOP (4±± mil)
DJ
TG
REFRESH
PART NUMBER
ADDRESSING PACKAGE REFRESH
• Timing
MT4LC8M8E1DJ-x
MT4LC8M8E1DJ-x S
MT4LC8M8E1TG-x
MT4LC8M8E1TG-x S
MT4LC8M8B6DJ-x
MT4LC8M8B6DJ-x S
MT4LC8M8B6TG-x
MT4LC8M8B6TG-x S
8K
8K
8K
8K
4K
4K
4K
4K
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
5±nꢂ acceꢂꢂ
6±nꢂ acceꢂꢂ
-5
-6
• Refꢁeꢂh Rateꢂ
Standaꢁd Refꢁeꢂh (64mꢂ ꢀeꢁipd)
Self Refꢁeꢂh (128mꢂ ꢀeꢁipd)
Npne
S*
NOTE: 1. The 8 Meg x 8 FPM DRAM baꢂe nsmbeꢁ
diffeꢁentiateꢂ the pffeꢁingꢂ in pne ꢀlace—
MT4LC8M8E1. The fifth field diꢂtingsiꢂheꢂ
vaꢁipsꢂ pꢀtipnꢂ: E1 deꢂignateꢂ an 8K ꢁefꢁeꢂh and
B6 deꢂignateꢂ a 4K ꢁefꢁeꢂh fpꢁ FPM DRAMꢂ.
2. The # ꢂꢃmbpl indicateꢂ ꢂignal iꢂ active LOW.
x = speed
GENERAL DESCRIPTION
*Cpntact factpꢁꢃ fpꢁ availabilitꢃ
The 8 Meg x 8 DRAMꢂ aꢁe high-ꢂꢀeed CMOS, dꢃ-
namic ꢁandpm-acceꢂꢂ mempꢁꢃ deviceꢂ cpntaining
67,1±8,864 bitꢂ pꢁganized in a x8 cpnfigsꢁatipn. The
8Megx8DRAMꢂaꢁefsnctipnallꢃpꢁganizedaꢂ8,388,6±8
lpcatipnꢂ cpntaining eight bitꢂ each. The 8,388,6±8
mempꢁꢃ lpcatipnꢂ aꢁe aꢁꢁanged in 8,192 ꢁpoꢂ bꢃ 1,±24
cplsmnꢂ fpꢁ the MT4LC8M8E1 pꢁ 4,±96 ꢁpoꢂ bꢃ 2,±48
cplsmnꢂfpꢁtheMT4LC8M8B6. DsꢁingREADpꢁWRITE
cꢃcleꢂ, each lpcatipn iꢂ sniqselꢃ addꢁeꢂꢂed via the
addꢁeꢂꢂ bitꢂ. Fiꢁꢂt, the ꢁpo addꢁeꢂꢂ iꢂ latched bꢃ the
Part Number Example:
MT4LC8M8E1DJ-5
KEY TIMING PARAMETERS
t
t
t
t
t
SPEED
RC
RAC
PC
AA
CAC
-5
-6
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000,MicronTechnology,Inc.
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