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MT4LC4M16N3TG-5 PDF预览

MT4LC4M16N3TG-5

更新时间: 2024-02-20 02:15:40
品牌 Logo 应用领域
镁光 - MICRON 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
24页 412K
描述
DRAM

MT4LC4M16N3TG-5 技术参数

生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP2,针数:50
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.83
访问模式:FAST PAGE WITH EDO最长访问时间:50 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码:R-PDSO-G50
JESD-609代码:e0长度:20.95 mm
内存密度:67108864 bit内存集成电路类型:EDO DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

MT4LC4M16N3TG-5 数据手册

 浏览型号MT4LC4M16N3TG-5的Datasheet PDF文件第2页浏览型号MT4LC4M16N3TG-5的Datasheet PDF文件第3页浏览型号MT4LC4M16N3TG-5的Datasheet PDF文件第4页浏览型号MT4LC4M16N3TG-5的Datasheet PDF文件第5页浏览型号MT4LC4M16N3TG-5的Datasheet PDF文件第6页浏览型号MT4LC4M16N3TG-5的Datasheet PDF文件第7页 
4 MEG x 16  
EDO DRAM  
MT4LC4M16R6, MT4LC4M16N3  
DRAM  
For the latest data sheet, please refer to the Micron Web  
site: www.micronsemi.com/mti/msp/html/datasheet.html  
FEATURES  
PIN ASSIGNMENT (To p Vie w )  
50-Pin TSOP  
• Sin gle +3.3V ±0.3V power supply  
• In dustry-stan dard x16 pin out, tim in g, fun ction s,  
an d package  
• 12 row, 10 colum n addresses (R6)  
13 row, 9 colum n addresses (N3)  
• High -perform an ce CMOS silicon -gate process  
• All in puts, outputs an d clocks are LVTTL-com patible  
• Exten ded Data-Out (EDO) PAGE MODE access  
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH  
distributed across 64m s  
VCC  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
DQ4  
DQ5  
DQ6  
DQ7  
NC  
VCC  
WE#  
RAS#  
NC  
NC  
NC  
NC  
A0  
A1  
A2  
A3  
A4  
A5  
VCC  
1
2
3
4
5
6
7
8
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
VSS  
DQ15  
DQ14  
DQ13  
DQ12  
VSS  
DQ11  
DQ10  
DQ9  
DQ8  
NC  
9
Option al self refresh (S) for low-power data  
reten tion  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
VSS  
CASL#  
CASH#  
OE#  
NC  
NC  
NC/A12†  
A11  
A10  
A9  
A8  
A7  
OPTIONS  
MARKING  
• Plastic Package  
50-pin TSOP (400 m il)  
TG  
• Tim in g  
50n s access  
60n s access  
-5  
-6  
A6  
VSS  
• Refresh Rates  
4K  
R6  
N3  
A12 for N3 version, NC for R6 version.  
8K  
Stan dard Refresh  
Self Refresh  
Non e  
S*  
MT4LC4M16R6 MT4LC4M16N3  
Configuration  
Refresh  
4 Meg x 16  
4K  
4 Meg x 16  
8K  
Operatin g Tem perature Ran ge  
Com m ercial (0°C to +70°C)  
Exten ded (-40°C to +85°C)  
Non e  
IT**  
Row Address  
Column Addressing  
4K (A0-A11)  
1K (A0-A9)  
8K (A0-A12)  
512 (A0-A8)  
NOTE: 1. The “#” symbol indicates signal is active LOW.  
*Contact factory for availability.  
**Available only on MT4LC4M16R6 standard refresh device.  
4 MEG x 16 EDO DRAM PART NUMBERS  
Part Number Example:  
REFRESH  
ADDRESSING PACKAGE REFRESH  
MT4LC4M16R6TG-5  
PART NUMBER  
MT4LC4M16R6TG-x  
MT4LC4M16R6TG-x S  
MT4LC4M16N3TG-x  
MT4LC4M16N3TG-x S  
4K  
4K  
8K  
8K  
400-TSOP Standard  
400-TSOP Self  
400-TSOP Standard  
400-TSOP Self  
KEY TIMING PARAMETERS  
t
t
t
t
t
t
SPEED  
RC  
RAC  
PC  
AA  
CAC  
CAS  
-5  
-6  
84ns  
50ns  
60ns  
20ns  
25ns  
25ns  
30ns  
13ns  
15ns  
8ns  
104ns  
10ns  
x = speed  
4 Meg x 16 EDO DRAM  
D29_2.p65 – Rev. 5/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
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