Datasheet > MT4LC4M16R6

MT4LC4M16R6

更新时间： 2024-01-16 01:45:00

品牌	Logo	应用领域
镁光 - MICRON		动态存储器
页数	文件大小	规格书
24页	473K
描述
DRAM

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中文翻译

获取价格

数据手册

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MT4LC4M16R6 数据手册

4 MEG x 16

EDO DRAM

MT4LC4M16R6, MT4LC4M16N3

DRAM

For the latest data sheet, please refer to the Micron Web

site: www.micron.com/products/datasheets/dramds.html

FEATURES

PIN ASSIGNMENT (To p Vie w )

50-Pin TSOP

• Single +3.3V ±±.3V ꢀpoeꢁ ꢂsꢀꢀlꢃ

• Indsꢂtꢁꢃ-ꢂtandaꢁd x16 ꢀinpst, timing, fsnctipnꢂ,

and ꢀackage

• 12 ꢁpo, 1± cplsmn addꢁeꢂꢂeꢂ (R6)

13 ꢁpo, 9 cplsmn addꢁeꢂꢂeꢂ (N3)

• High-ꢀeꢁfpꢁmance CMOS ꢂilicpn-gate ꢀꢁpceꢂꢂ

• All inꢀstꢂ, pstꢀstꢂ and clpckꢂ aꢁe LVTTL-cpmꢀatible

• Extended Data-Ost (EDO) PAGE MODE acceꢂꢂ

• 4,±96-cꢃcle CAS#-BEFORE-RAS# (CBR) REFRESH

diꢂtꢁibsted acꢁpꢂꢂ 64mꢂ

VSS

DQ0

DQ1

DQ2

DQ3

DQ15

DQ14

DQ13

DQ12

VSS

DQ4

DQ5

DQ6

DQ7

DQ11

DQ10

DQ9

DQ8

• Oꢀtipnal ꢂelf ꢁefꢁeꢂh (S) fpꢁ lpo-ꢀpoeꢁ data

ꢁetentipn

VSS

WE#

RAS#

CASL#

CASH#

OE#

OPTIONS

MARKING

• Plaꢂtic Package

5±-ꢀin TSOP (4±± mil)

NC/A12^†

A11

A10

• Timing

5±nꢂ acceꢂꢂ

6±nꢂ acceꢂꢂ

-5

-6

VSS

• Refꢁeꢂh Rateꢂ

†

A12 for N3 version, NC for R6 version.

Standaꢁd Refꢁeꢂh

Self Refꢁeꢂh

Npne

MT4LC4M16R6 MT4LC4M16N3

Configuration

Refresh

Row Address

Column Addressing

4 Meg x 16

4K (A0-A11)

1K (A0-A9)

4 Meg x 16

8K (A0-A12)

512 (A0-A8)

• Oꢀeꢁating Temꢀeꢁatsꢁe Range

Cpmmeꢁcial (±°C tp +7±°C)

Npne

NOTE: 1. The “#” symbol indicates signal is active LOW.

*Contact factory for availability.

Part Number Example:

4 MEG x 16 EDO DRAM PART NUMBERS

MT4LC4M16R6TG-5

REFRESH

PART NUMBER

ADDRESSING PACKAGE REFRESH

MT4LC4M16R6TG-x

MT4LC4M16R6TG-x S

MT4LC4M16N3TG-x

MT4LC4M16N3TG-x S

400-TSOP Standard

400-TSOP Self

400-TSOP Standard

400-TSOP Self

KEY TIMING PARAMETERS

SPEED

RAC

CAC

CAS

-5

-6

84ns

104ns

50ns

60ns

20ns

25ns

30ns

13ns

15ns

8ns

10ns

x = speed

4 Meg x 16 EDO DRAM

D29_C.p65 – Rev. 2/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

12 3 4 5 6 7...24

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