1 MEG x 16
FPM DRAM
MT4C1M16C3, MT4LC1M16C3
FPM DRAM
For the latest data sheet revisions, please refer to the Micron
Website:www.micron.com/datasheets
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate
process
PINASSIGNMENT(TopView)
42-PinSOJ
44/50-PinTSOP
• Single power supply (+3.3V ±±.3V or ꢀV ±±.ꢀV5
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR5 and HIDDEN
• Optional self refresh (S5 for low-power data
retention
• BYTE WRITE and BYTE READ access cycles
• 1,±24-cycle refresh (1± row, 1± column addresses5
• FAST-PAGE-MODE (FPM5 access
V
CC
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
VSS
V
CC
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
V
CC
VSS
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
V
CC
V
SS
9
10
11
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
9
10
11
12
13
14
15
16
17
18
19
20
21
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
VSS
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
OPTIONS
• Voltage1
3.3V
MARKING
LC
C
CC
ꢀV
A4
VSS
CC
• Packages
Plastic SOJ (4±± mil5
Plastic TSOP (4±± mil5
DJ
TG
NOTE: The # symbol indicates signal is active LOW.
• Timing
1 MEG x 16 FPM DRAM PART NUMBERS
ꢀ±ns access
6±ns access
-ꢀ
-6
PART NUMBER
SUPPLY PACKAGE REFRESH
• Refresh Rates
MT4LC1M16C3DJ-6
MT4LC1M16C3DJ-6 S
MT4LC1M16C3TG-6
MT4LC1M16C3TG-6 S
MT4C1M16C3DJ-6
MT4C1M16C3TG-6
3.3V
3.3V
3.3V
3.3V
5V
SOJ
SOJ
TSOP
TSOP
SOJ
Standard
Self
Standard
Self
Standard
Standard
Standard Refresh (16ms period5
Self Refresh (128ms period5
None
S2
• OperatingTemperatureRange
Commercial (0oC to +70oC)
Extended (-20oC to +80oC)
None
ET3
5V
TSOP
Part Number Example:
MT4LC1M16C3DJ-5
GENERALDESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#5. These function identi-
cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#5 to transition LOW and
NOTE: 1. The third field distinguishes the low voltage offering:
LC designates VCC = 3.3V and C designates VCC = 5V.
2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)
KEYTIMINGPARAMETERS
t
t
t
t
t
t
SPEED
-5
-6
RC
RAC
PC
AA
CAC
RP
84ns
110ns
50ns
60ns
20ns
35ns
25ns
30ns
15ns
15ns
30ns
40ns
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
1