‡
ADVANCE
1 MEG x 16
3V ENHANCED+ BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F160C34
FEATURES
• Thirty-nine erase blocks:
BALL ASSIGNMENT (Top View)
46-Ball FBGA
Eight 4K-word parameter blocks
Thirty-one 32K-word main memory blocks
• VCC, VCCQ and VPP voltages:
3.3V ±5% VCC
3.3V ±5% VCCQ
1.65V–3.465V and 12V VPP
1
2
3
4
5
6
7
8
• Address access times:
A13
A11
A8
V
PP
WP#
A19
A7
A4
A
B
C
D
E
90ns at 3.3V ±5%
• Low power consumption:
Standby and deep power-down mode < 1µA
(typical ICC)
Automatic power saving feature (APS mode)
• Enhanced WRITE/ERASE SUSPEND (1µs typical)
• 128-bit OTP area for security purposes
• Industry-standard command set compatibility
• Software/hardware block protection
A14
A15
A16
A10
A12
WE#
A9
RP#
A18
A17
A6
A5
A3
A2
A1
A0
DQ14
DQ15
DQ7
DQ5
DQ6
DQ13
DQ2
DQ3
DQ8
DQ9
DQ10
CE#
DQ0
DQ1
DQ11
DQ12
DQ4
V
CC
Q
VSS
V
SS
V
CC
OE#
F
OPTIONS
• Timing
NUMBER
90ns access
-9
(Ball Down)
• Boot Block Starting Address
Top (FFFFFh)
T
B
NOTE: See page 3 for Ball Description Table.
Bottom (00000h)
See last page for mechanical drawing.
• Package
46-ball FBGA (6 x 8 ball grid)
FD
ET
• Temperature Range
WSM status can be monitored by an on-chip status reg-
ister to determine the progress of program/erase tasks.
The device is equipped with 128 bits of one time
programmable (OTP) area. The soft protection feature
forblockswillmarkthemasread-onlybyconfiguringsoft
protection registers with command sequences.
Extended (-40ºC to +85ºC)
Part Number Example:
MT28F160C34FD-9 TET
GENERAL DESCRIPTION
The MT28F160C34 is a nonvolatile, electrically block-
erasable (flash), programmable memory containing
16,777,216 bits organized as 1,048,576 words (16 bits).
The MT28F160C34 is manufactured on 0.22µm process
technology in a 46-ball FBGA package.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM), which simplifies these operations and
relieves the system processor of secondary tasks. The
ARCHITECTURE
The MT28F160C34 flash contains eight 4K-word
parameter blocks and thirty-one 32K-word blocks.
Memory is organized by using a blocked architecture to
allow independent erasure of selected memory blocks.
Any address within a block address range selects that
block for the required READ, WRITE, or ERASE operation
(see Figure 1).
1Megx163VEnhanced+BootBlockFlashMemory
MT28F160C34_3.p65 – Rev. 3, Pub. 8/01
©2001,MicronTechnology,Inc.
1
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.