Datasheet > MT28EW512ABA1HPC-1SIT

MT28EW512ABA1HPC-1SIT

更新时间： 2024-04-09 18:58:03

品牌	Logo	应用领域
镁光 - MICRON		/
页数	文件大小	规格书
81页	1091K
描述
Legacy NOR Flash

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中文翻译

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数据手册

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MT28EW512ABA1HPC-1SIT 数据手册

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512Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR

Features

List of Figures

Figure 1: Part Number Chart ............................................................................................................................ 2

Figure 2: Logic Diagram ................................................................................................................................... 8

Figure 3: 56-Pin TSOP (Top View) .................................................................................................................... 9

Figure 4: 64-Ball LBGA (Top View – Balls Down) ............................................................................................. 10

Figure 5: 56-Ball VFBGA (Top View – Balls Down) ........................................................................................... 11

Figure 6: Data Polling Flowchart .................................................................................................................... 19

Figure 7: Toggle Bit Flowchart ........................................................................................................................ 20

Figure 8: Data Polling/Toggle Bit Flowchart .................................................................................................... 21

Figure 9: Lock Register Program Flowchart ..................................................................................................... 23

Figure 10: Boundary Condition of Program Buffer Size .................................................................................... 34

Figure 11: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 35

Figure 12: Software Protection Scheme .......................................................................................................... 44

Figure 13: Set/Clear Nonvolatile Protection Bit Algorithm Flowchart ............................................................... 50

Figure 14: Power-Up Timing .......................................................................................................................... 57

Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 58

Figure 16: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 58

Figure 17: AC Measurement Load Circuit ....................................................................................................... 60

Figure 18: AC Measurement I/O Waveform ..................................................................................................... 60

Figure 19: Random Read AC Timing (8-Bit Mode) ........................................................................................... 64

Figure 20: Random Read AC Timing (16-Bit Mode) ......................................................................................... 65

Figure 21: BYTE# Transition Read AC Timing .................................................................................................. 65

Figure 22: Page Read AC Timing (16-Bit Mode) ............................................................................................... 66

Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 68

Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 69

Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 71

Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 72

Figure 27: Chip/Block Erase AC Timing (16-Bit Mode) .................................................................................... 73

Figure 28: Accelerated Program AC Timing ..................................................................................................... 73

Figure 29: Data Polling AC Timing .................................................................................................................. 74

Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing .............................................................................. 75

Figure 31: 56-Pin TSOP – 14mm x 20mm (Package Code: JS) ............................................................................ 78

Figure 32: 64-Ball LBGA – 11mm x 13mm (Package Code: PC) ......................................................................... 79

Figure 33: 56-Ball VFBGA – 7mm x 9mm (Package Code: PN) .......................................................................... 80

PDF: 09005aef855e354a

mt28ew_generation-b_512mb.pdf - Rev. I 05/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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与MT28EW512ABA1HPC-1SIT相关器件

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