Datasheet > MSM548333

MSM548333

更新时间： 2022-12-13 04:56:09

品牌	Logo	应用领域
冲电气 - OKI		存储
页数	文件大小	规格书
42页	418K
描述
240,384-Word x 8-bit + 240,384-Word x 4-bit Triple Port type Field Memory

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MSM548333 数据手册

¡ Semiconductor

MSM548333

RADE1/RX : Read Address Enable for Y1 and C1/Read X Address Reset Logic Function

RADE1/RXisadualfunctioncontrolinput. RADE1, oneofthetwofunctionsofRADE1/RX, isaread

addressenableinputforY1andC1. Inthereadaddresssetcycle, definedbyRR1/TRlow, Xaddress

(orlineaddress)andYaddress(orbitaddressinacertainline)inputfromtheRXAD1pinandRYAD1

pinarelatchedintointernalreadXaddressregisterandYaddressregister,respectivelysynchronously

with RCLK.

RX, thesecondfunctionofRADE1/RX, worksasanelementtosetreadXaddress(orlineaddress)

resetmode.Inanaddressresetmodecycle,definedbyRR1/TRlevelhigh,RXworksasoneofinputs

which form several read reset logic as shown in the "FUNCTION TABLE for read".

RXAD1 : Read X Address for Y1 and C1

RXAD1isareadXaddress(orlineaddress)inputforY1andC1. RXAD1specifiesthelineaddress.

9 bits of read X address data are input serially from RXAD1.

RYAD1 : Read Y Address for Y1 and C1

RYAD1 is a read Y address (or bit address in a certain line) input for Y1 and C1. RYAD1 specifies the

firstbitaddressofconsecutiveserialreaddatainthelinewhoselineaddressisdefinedbytheXread

address from RXAD1. 10 bits of Y address data are input serially from RYAD1.

RR2/TR : Read Reset for Y2 and C2

RR2/TR is a read reset control input for Y2 and C2. Read address reset modes for Y2 and C2 are

defined when RR2/TR level is high based on the "FUNCTION TABLE for read".

RXINC2 : Read X Address Increment for Y2 and C2

RXINC2 is a read X address (or line address) increment control input for Y2 and C2. In the read

address reset cycle, defined by RR2/TR high, the common read X address (or line address) for Y2

and C2 is incremented by RXINC2.

RADE2/RX : Read Address Enable for Y2 and C2/Read X Address Reset Logic Function

RADE2/RXisadualfunctioncontrolinput. RADE2, oneofthetwofunctionsofRADE2/RX, isaread

address enable input for Y2 and C2. In the read address set cycle, defined by RR2/TR high, the read

Xaddress(orlineaddress)andthereadYaddress(orbitaddressinacertainline), whichareinput

from the RXAD2, RYADY2 and RYADC2 pins, are latched into internal read X address register and

read Y address register, respectively, synchronously with RCLK.

RX, the second function of RADE2/RX, performs a function for setting the read X address (or line

address) reset mode. In a read address reset mode cycle, defined by RR2/TR level high, RX works

asoneofinputswhichformseveralreadresetlogicasshowninthe"FUNCTIONTABLEforread".

RXAD2 : Read X Address for Y2 and C2

RXAD2isareadXaddress(orlineaddress)inputforY2andC2. RXAD2specifiesthelineaddress.

9 bits of X address data is input serially from RXAD2.

RYADY2 : Read Y Address for Y2

RYADY2 is a read Y address (or bit address in a certain line) input for Y2. RYADY2 specifies the first

bitaddressofserialreaddatainthelinewhoselineaddressisspecifiedbytheXaddressRXAD2.

10 bits of Y address data are input serially from RYADY2.

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与MSM548333相关器件

型号	品牌	描述	获取价格	数据表
MSM548512D-10GS	OKI	Pseudo Static RAM, 512KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SSOP-32	获取价格
MSM548512D-10RS	OKI	Pseudo Static RAM, 512KX8, 100ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格
MSM548512D-12GS	OKI	Pseudo Static RAM, 512KX8, 120ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SSOP-32	获取价格
MSM548512D-12RS	OKI	Pseudo Static RAM, 512KX8, 120ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格
MSM548512D-80RS	OKI	Pseudo Static RAM, 512KX8, 80ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格
MSM548512L	OKI	524,288-Word X 8-Bit High-Speed PSRAM	获取价格

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