¡ Semiconductor
MSM548333
PIN FUNCTION (Note : Y1 = "port-1 of Y area", Y2 = "port-2 of Y area", C1 = "port-1 of C area",
C2 = "port-2 of C area "
READ RELATED
RCLK : Read Clock for Y1 and C1, Common Read Address Strobe Clock
RCLK is the read control clock input for Y1 and C 1. Synchronized with RCLK's rising edge, serial
readaccessfromY1andC1isexecutedwhenRE1/RYishigh. (Notethatthewriteporthasoneport,
Y and C, but the read port has dual ports, Y1 and C1 plus Y2 and C2. Y1 and C1 are controlled by the
common read clock RCLK. But Y2 and C2 are controlled by separated read clocks, RCLKY2 and
RCLKC2, asynchronously.)
The internal counter for the serial read address is incremented automatically on the rising edge of
RCLK.Inareadaddresssetcycle,allthereadaddressbitswhichwereinputfromeachRXAD1,RYAD1,
RXAD2, RYADY2, and RYADC2 pins are stored into internal address registers synchronized
withRCLK.Inthisaddresssetcycle,RADE1/RXandRADE2/RXmustbeheldhighandtheRR1/
TR and RR2/TR must be held low.
In the read address reset cycle, various read address reset modes can be set synchronously with
RCLK. Theseresetcyclesworktoreplacecomplicatedserialaddresscontrolwhichrequiresmany
RCLKclockswithasimpleresetcyclecontrolrequiringonlyasingleRCLKcycle.Itgreatlyfacilitates
memory access.
RE1/RY : Read Enable for Y1 and C1/Read Y Address Reset Logic Function
RE1/RY is a dual function control input. RE1, one of the two functions of RE1/RY, is read enable.
RE1enablesordisablesbothinternalreadaddresspointersanddata-outbuffersofY1andC1.When
RE1/RYishigh, theinternalreadaddresspointerforY1andC1isincrementedsynchronouslywith
RCLK. When RE1/RY is low, even if the RCLK is input, the internal read address pointer is not
incremented.
RY,thesecondfunctionofRE1/RY,performsafunctionforsettingthereadYaddress(orbitaddress
in a certain line) reset mode in Y1 and C1. In a read address reset mode cycle, as defined by RR1/TR
being high, RY works as one of inputs which form several read reset logic as shown in the
"FUNCTION TABLE for read". In the address reset cycle, when RE1/RY level is low, each Y1and C1
internalreadYaddressisresetto0. WhenRE1/RYishigh, eachY1andC1internalreadYaddress
is reset to the respective address which was set in the previous read address set cycle.
DOY1/0-7 : Data-Outs for Y1
DOY1/0-7areserialdata-outsforY1.Eachcorrespondingdataoutbuffer'impedanceiscontrolled
by RE1/RY.
DOC1/0-3 : Data-Outs for C1
DOC1/0-3 are serial data-outs for C1. Each corresponding data out buffer' impedance is controlled
by RE1/RY.
RR1/TR : Read Reset for Y1 and C1
RR1/TRisareadresetcontrolinputforY1andC1.ReadaddressresetmodesaredefinedwhenRR1/
TR level is high according to the "FUNCTION TABLE for read".
RXINC1 : Read X Address Increment for Y1 and C1
RXINC1 is a read X address (or line address) increment control input for Y1 and C1. In the read
address reset cycle, defined by RR1/TR high, the common X address (or line address) for Y1 and C1
is incremented by RXINC1.
6/42
5秒后页面跳转
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
