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MSM514221B-30JS PDF预览

MSM514221B-30JS

更新时间: 2024-11-08 22:35:23
品牌 Logo 应用领域
冲电气 - OKI 存储内存集成电路光电二极管
页数 文件大小 规格书
15页 154K
描述
262,263-Word x 4-Bit Field Memory

MSM514221B-30JS 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:20
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.8Is Samacsys:N
其他特性:INTERNAL 4 X 512 ROWS X 512 COLUMNS OF DRAM CELLS; SELF REFRESHJESD-30 代码:R-PDSO-J20
长度:17.15 mm内存密度:1048576 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:4
功能数量:1端子数量:20
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
座面最大高度:3.55 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MSM514221B-30JS 数据手册

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E2L0029-17-Y1  
This version: Jan. 1998  
Previous version: Dec. 1996  
¡ Semiconductor  
MSM514221B  
262,263-Word ¥ 4-Bit Field Memory  
DESCRIRTION  
The OKI MSM514221B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed  
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital  
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity  
TVs and VTRs, exclusively. The MSM514221B is not designed for the other use or high end use  
in medical systems, professional graphics systems which require long term picture, and data  
storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen.  
Each of the 4-bit planes has separate serial write and read ports. These employ independent  
control clocks to support asynchronous read and write operations. Different clock rates are also  
supported that allow alternate data rates between write and read data streams.  
The MSM514221B provides high speed FIFO, First-In First-Out, operation without external  
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the  
users.  
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial  
access operation, so that the serial read and/or write control clock can be halted high or low for  
any duration as long as the power is on. Internal conflicts of memory access and refreshing  
operations are prevented by special arbitration logic.  
The MSM514221B's function is simple, and similar to a digital delay device whose delay-bit-  
length is easily set by reset timing. The delay length, number of read delay clocks between write  
and read, is determined by externally controlled write and read reset timings.  
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high  
speed first-bit-access with no clock delay just after the write or read reset timings.  
The MSM514221B is similar in operation and functionality to OKI 2-Mbit Field Memory  
MSM518221.  
1/15  

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Memory Circuit, 256KX4, CMOS, PDSO20, 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOJ-26/20