Datasheet > MSM514222B-40ZS

MSM514222B-40ZS

更新时间： 2024-11-10 04:48:19

品牌	Logo	应用领域
冲电气 - OKI		/
页数	文件大小	规格书
15页	154K
描述
Memory Circuit, 256KX4, CMOS, PZIP20, 0.400 INCH, 1.27 MM PITCH, PLASTIC, ZIP-20

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MSM514222B-40ZS 数据手册

E2L0030-17-Y1

This version: Jan. 1998

Previous version: Dec. 1996

¡ Semiconductor

MSM514222B

¡ Semiconductor

MSM514222B

262,263-Word ¥ 4-Bit Field Memory

DESCRIRTION

The OKI MSM514222B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory. It is designed

for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital

movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity

TVs and VTRs, exclusively. The MSM514222B is not designed for the other use or high end use

in medical systems, professional graphics systems which require long term picture, and data

storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen

and cascaded directly without any delay devices among the MSM514222B. (Cascading of

MSM514222B provides larger storage depth or a longer delay).

Each of the 4-bit planes has separate serial write and read ports. These employ independent

control clocks to support asynchronous read and write operations. Different clock rates are also

supported that allow alternate data rates between write and read data streams.

The MSM514222B provides high speed FIFO, First-In First-Out, operation without external

refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the

users.

Moreover, fully static type memory cells and decoders for serial access enable refresh free serial

access operation, so that the serial read and/or write control clock can be halted high or low for

any duration as long as the power is on. Internal conflicts of memory access and refreshing

operations are prevented by special arbitration logic.

The MSM514222B's function is simple, and similar to a digital delay device whose delay-bit-

length is easily set by reset timing. The delay length, number of read delay clocks between write

and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high

speed first-bit-access with no clock delay just after the write or read reset timings.

The MSM514222B is similar in operation and functionality to OKI 2-Mbit Field Memory

MSM518222.

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与MSM514222B-40ZS相关器件

型号	品牌	获取价格	描述	数据表
MSM514222B-60JS	OKI	获取价格	Memory IC, CMOS, PDSO20
MSM514222B-60RS	OKI	获取价格	Memory Circuit, 256KX4, CMOS, PDIP16, 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-16
MSM514222B-60ZS	OKI	获取价格	Memory IC, CMOS, PZIP20
MSM514223B	OKI	获取价格	262,263-Word x 4-Bit Field Memory
MSM514223B-30RS	OKI	获取价格	Memory Circuit, 256KX4, CMOS, PDIP18, 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-18
MSM514223B-40RS	OKI	获取价格	Memory Circuit, 256KX4, CMOS, PDIP18, 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-18
MSM514223B-60RS	OKI	获取价格	Memory Circuit, 256KX4, CMOS, PDIP18, 0.300 INCH, 2.54 MM PITCH, PLASTIC, DIP-18
MSM514252A	OKI	获取价格	262,144-Word x 4-Bit Multiport DRAM
MSM514252A-10ZS	OKI	获取价格	262,144-Word x 4-Bit Multiport DRAM
MSM514252A-70ZS	OKI	获取价格	Video DRAM, 256KX4, 70ns, CMOS, PZIP28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, ZIP-28

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