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MSC8251TAG1000B PDF预览

MSC8251TAG1000B

更新时间： 2024-11-30 21:16:07
品牌 Logo 应用领域
恩智浦 - NXP PC双倍数据速率外围集成电路
页数 文件大小 规格书
68页 851K
描述
StarCore DSP, 1x 1GHz SC3850 cores, DDR2/3, SRIO, PCIe, QE, GbE, -40-105C

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MSC8251TAG1000B 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred包装说明：29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
Reach Compliance Code：compliantECCN代码：3A991.A.1
HTS代码：8542.31.00.01风险等级：5.73
桶式移位器：NO边界扫描：YES
格式：FIXED POINT内部总线架构：SINGLE
JESD-30 代码：S-PBGA-B783JESD-609代码：e1
长度：29 mm低功率模式：YES
湿度敏感等级：3端子数量：783
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：245座面最大高度：3.94 mm
最大供电电压：1.05 V最小供电电压：0.97 V
标称供电电压：1 V表面贴装：YES
技术：CMOS端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：29 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

MSC8251TAG1000B 数据手册

 浏览型号MSC8251TAG1000B的Datasheet PDF文件第2页浏览型号MSC8251TAG1000B的Datasheet PDF文件第3页浏览型号MSC8251TAG1000B的Datasheet PDF文件第4页浏览型号MSC8251TAG1000B的Datasheet PDF文件第5页浏览型号MSC8251TAG1000B的Datasheet PDF文件第6页浏览型号MSC8251TAG1000B的Datasheet PDF文件第7页 
Freescale Semiconductor  
Data Sheet  
Document Number: MSC8251  
Rev. 7, 08/2013  
MSC8251  
FC-PBGA–783  
29 mm × 29 mm  
Single-Core Digital Signal  
Processor  
•
One StarCore SC3850 DSP subsystems, with an SC3850 DSP  
core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,  
unified 512 Kbyte L2 cache configurable as M2 memory in  
64 Kbyte increments, memory management unit (MMU),  
extended programmable interrupt controller (EPIC), two  
general-purpose 32-bit timers, debug and profiling support,  
low-power Wait, Stop, and power-down processing modes, and  
ECC/EDC support.  
Chip-level arbitration and switching system (CLASS) that  
provides full fabric non-blocking arbitration between the cores  
and other initiators and the M2 memory, shared M3 memory,  
DDR SRAM controllers, device configuration control and status  
registers, and other targets.  
•
High-speed serial interface that supports two Serial RapidIO  
interfaces, one PCI Express interface, and two SGMII interfaces  
(multiplexed). The Serial RapidIO interfaces support 1x/4x  
operation up to 3.125 Gbaud with a single messaging unit and two  
DMA units. The PCI Express controller supports 32- and 64-bit  
addressing, x4, x2, and x1 link.  
QUICC Engine technology subsystem with dual RISC  
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction  
RAM, supporting two communication controllers for two Gigabit  
Ethernet interfaces (RGMII or SGMII), to offload scheduling  
tasks from the DSP cores, and an SPI.  
I/O Interrupt Concentrator consolidates all chip maskable  
interrupt and non-maskable interrupt sources and routes then to  
INT_OUT, NMI_OUT, and the cores.  
UART that permits full-duplex operation with a bit rate of up to  
6.25 Mbps.  
•
•
•
•
1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can  
be turned off to save power.  
96 Kbyte boot ROM.  
•
•
•
•
•
•
Three input clocks (one global and two differential).  
Five PLLs (three global and two Serial RapidIO PLLs).  
Two DDR controllers with up to a 400 MHz clock (800 MHz data  
rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to  
four banks (two per controller) and support for DDR2 and DDR3.  
DMA controller with 32 unidirectional channels supporting 16  
memory-to-memory channels with up to 1024 buffer descriptors  
per channel, and programmable priority, buffer, and multiplexing  
configuration. It is optimized for DDR SDRAM.  
Up to four independent TDM modules with programmable word  
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,  
up to 62.5 Mbps data rate for each TDM link, and with glueless  
interface to E1 or T1 framers that can interface with  
H-MVIP/H.110 devices, TSI, and codecs such as AC-97.  
Two general-purpose 32-bit timers for RTOS support per SC3850  
core, four timer modules with four 16-bit fully programmable  
timers, and eight software watchdog timers (SWT).  
Eight programmable hardware semaphores.  
•
•
Up to 32 virtual interrupts and a virtual NMI asserted by simple  
write access.  
•
•
•
•
I2C interface.  
Up to 32 GPIO ports, sixteen of which can be configured as  
external interrupts.  
•
Boot interface options include Ethernet, Serial RapidIO interface,  
I2C, and SPI.  
•
•
Supports standard JTAG interface  
Low power CMOS design, with low-power standby and  
power-down modes, and optimized power-management circuitry.  
45 nm SOI CMOS technology.  
•
© 2010–2013 Freescale Semiconductor, Inc.  
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与MSC8251TAG1000B相关器件

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 		orderDual-Core Digital Signal Processor
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 		Quad-Core Digital Signal Processor
MSC8254_11 FREESCALE

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 		Quad-Core Digital Signal Processor
MSC8254SAG1000B NXP

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 		StarCore DSP, 4x 1GHz SC3850 cores, DDR2/3, SRIO, PCIe, QE, GbE, 0-105C
MSC8254SVT1000B FREESCALE

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 		Quad-Core Digital Signal Processor
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