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MPC905DR2 PDF预览

MPC905DR2

更新时间: 2024-02-06 04:50:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
5页 92K
描述
50MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16, PLASTIC, SOIC-16

MPC905DR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm端子数量:16
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:50 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):225
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.3 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

MPC905DR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC905/D  
The MPC905 is a six output clock generation device targeted to pro-  
vide the clocks required in a 3.3V or 5.0V PCI environment. The device  
operates from a 3.3V supply and can interface to either a TTL input or an  
external crystal. The inputs to the device can be driven with 5.0V when  
the VCC is at 3.3V. The outputs of the MPC905 meet all of the specifica-  
tions of the PCI standard.  
1:6 PCI  
CLOCK GENERATOR/  
FANOUT BUFFER  
Six Low Skew Outputs  
Synchronous Output Enables for Power Management  
Low Voltage Operation  
XTAL Oscillator Interface  
16-Lead SOIC Package  
5.0V Tolerant Enable Inputs  
The MPC905 device is targeted for PCI bus or processor bus environ-  
ments with up to 12 clock loads. Each of the six outputs on the MPC905  
can drive two series terminated 50transmission lines. This capability  
effectively makes the MPC905 a 1:12 fanout buffer.  
16  
1
The MPC905 offers two synchronous enable inputs to allow users flex-  
ibility in developing power management features for their designs. Both  
enable signals are active HIGH inputs. A logic ‘0’ on the Enable1 will pull  
outputs 0 to 4 into the logic ‘0’ state. A logic ‘1’ on the Enable1 input will  
result in outputs 0 to 4 to be toggling. A logic ‘0’ on Enable2 will cause  
output BLK5 to a logic ‘0’ state, whereas a logic ‘1’ on Enable2 will cause  
output BLK5 to toggle. The oscillator remains on.  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751B  
6
The Enable2 input can be used to disable any high power device for system power savings during periods of inactivity. Both  
enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already  
LOW. This feature guarantees no runt pulses will be generated during enabling and disabling.  
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Pinout: 16-Lead Plastic Package (Top View)  
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Rev 2  
528  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  

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