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MPC9109 PDF预览

MPC9109

更新时间: 2024-01-22 15:23:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟
页数 文件大小 规格书
8页 253K
描述
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

MPC9109 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFP包装说明:7 X 7 MM, 0.80 MM PITCH, TQFP-32
针数:32Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.43
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:9109
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.02 A
湿度敏感等级:2功能数量:1
反相输出次数:端子数量:32
实输出次数:18最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):220电源:3.3 V
传播延迟(tpd):4.9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm

MPC9109 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC9109/D  
The MPC9109 is a 1:18 low voltage clock distribution chip with 2.5V or  
3.3V LVCMOS output capabilities. The device features the capability to  
select either a differential LVPECL or an LVCMOS compatible input. The  
18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive  
strength to drive 50series or parallel terminated transmission lines.  
With output–to–output skews of 200ps, the MPC9109 is ideal as a clock  
distribution chip for the most demanding of synchronous systems. The  
2.5V outputs also make the device ideal for supplying clocks for a high  
performance Pentium II microprocessor based design. For a higher  
performance version of the 9109 refer to the MPC940L data sheet.  
LOW VOLTAGE  
1:18 CLOCK  
DISTRIBUTION CHIP  
LVPECL or LVCMOS Clock Input  
2.5V LVCMOS Outputs for Pentium II Microprocessor Support  
200ps Maximum Output–to–Output Skew @ 3.3V Output  
Maximum Output Frequency of 250MHz @ 3.3V Core  
32–Lead QFP Packaging  
Dual or Single Supply Device:  
FA SUFFIX  
32–LEAD QFP PACKAGE  
CASE 873A–02  
Dual V  
Supply Voltage, 3.3V Core and 2.5V Output  
CC  
Single 3.3V V  
Single 2.5V V  
Supply Voltage for 3.3V Outputs  
Supply Voltage for 2.5V I/O  
CC  
CC  
With a low output impedance (20), in both the HIGH and LOW logic  
states, the output buffers of the MPC9109 are ideal for driving series  
terminated transmission lines. With a 20output impedance the 9109  
has the capability of driving two series terminated lines from each output.  
This gives the device an effective fanout of 1:36. If a lower output  
impedance is desired please see the MPC942 data sheet. If better  
performance is desired please see the MPC940L data sheet.  
The differential LVPECL inputs of the MPC9109 allow the device to interface directly with a LVPECL fanout buffer like the  
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a  
more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the  
two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the  
LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the MPC9109 have internal pullup/pulldown  
resistor so they can be left open if unused.  
The MPC9109 is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can  
operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32–lead  
QFP package was chosen to optimize performance, board space and cost of the device. The 32–lead TQFP has a 7x7mm body  
size with a conservative 0.8mm pin spacing.  
Pentium II is a trademark of Intel Corporation.  
3/99  
For More Information On This RPErVo1d.0uct,  
Motorola, Inc. 1999  
Go to: www.freescale.com  

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