Datasheet > MPC9100

MPC9100

更新时间： 2024-02-14 21:42:44

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟发生器
页数	文件大小	规格书
8页	115K
描述
DUAL PLL CLOCK GENERATOR

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中文翻译

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技术参数
数据手册

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MPC9100 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, QFP32,.35SQ,32	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	Base Number Matches：	1

MPC9100 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC9100 is a dual PLL phase locked loop clock generator. The

device synthesizes a 14.318 MHz input reference to provide a buffered

copy of the input reference, a 31.3344MHz clock output and a 45.1584

clock output.

The device features a fully integrated crystal oscillator as the clock

reference source. No external components are required other than the

14.318 MHz crystal. The TCLK input is used only for factory test and

cannot be used as the PLL clock reference. To reduce total die area the

PLL loop filter capacitors are brought outside the chip. The FCAP pins are

used to connect these capacitors to the internal PLL’s. 0.01µf capacitors

are recommended.

DUAL PLL

CLOCK GENERATOR

The device features three synchronous output enable pins to allow for

shutting down specific clocks. When driven to a logic LOW the OE pins

will freeze the selected clock in its low state. Internal timing has been

established that guarantee transition into and out of the freeze state will

not produce output glitches. These control inputs have internal pull up

resistors so that they will default to the output active state.

The TEST0–2 pins allow for the testing of the internal logic of the

device. Most of the states are reserved for factory test use with one

exception. When the TEST 0 pin is driven low the internal state machines

will be reset and the outputs will be driven into high impedance. The

TEST pins also have internal pull up resistors such that they will default

into the normal operation mode of the chip.

FA SUFFIX

TQFP PACKAGE

CASE 873A–02

The MPC9100 features separate internal power buses to try to isolate

the output noise from the internal PLL’s and the other outputs. The VCCA

pins are the power supply pins for the analog PLL’s, the VCCI pin is the

power supply for the internal core logic and the VCCO’s are the power

pins for the output buffers. All of these pins should be tied to a common

power plane on the printed circuit board.

FUNCTION TABLES

PIN DESCRIPTION

TEST2

TEST1

TEST0

Function

Description

Factory Test

Q_31

Q_14

Q_45

VCCO_XX

GNDO_XX

VCCI

31.3344MHz Output

14.318MHz Output

45.1584MHz Output

Output Buffer Power Supply

Output Buffer Ground

Core Logic Power Supply

Core Logic Ground

PLL Power Supply

PLL Ground

Crystal Oscillator Input

LVCMOS Reference Clock Input

PLL Filter Capacitor Input

Factory Test

Master Reset/Tristate

Normal Operation

GNDI

VCCAX

GNDAX

XTAL1

XTAL2

TCLK

OE_XX

Function

FCAPXX

FCAPXXP

Output LOW

Output Active

10/96

Motorola, Inc. 1996

REV 0

12 3 4 5 6 7 8

中文翻译

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与MPC9100相关器件

型号	品牌	获取价格	描述	数据表
MPC9108	MOTOROLA	获取价格	MULTIPLE OUTPUT CLOCK SYNTHESIZER
MPC9108DR2	MOTOROLA	获取价格	50MHz, OTHER CLOCK GENERATOR, PDSO8, PLASTIC, SOIC-8
MPC9109	MOTOROLA	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC9109	IDT	获取价格	Low Voltage 1:18 Clock Distribution Chip
MPC9109ACR2	NXP	获取价格	9109 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9109FA	IDT	获取价格	LOW SKEW CLOCK DRIVER, PQFP32, 7 X 7 MM, 0.80 MM PITCH, TQFP-32
MPC9109FAR2	MOTOROLA	获取价格	Low Skew Clock Driver, PQFP32, 7 X 7 MM, 0.80 MM PITCH, TQFP-32
MPC9109FAR2	IDT	获取价格	Processor Specific Clock Generator, 250MHz, PQFP32, 7 X 7 MM, 0.80 MM PITCH, TQFP-32
MPC910FA	MOTOROLA	获取价格	Low Skew Clock Driver, MPC900 Series, 18 True Output(s), 0 Inverted Output(s), PQFP32, TQF
MPC911	MOTOROLA	获取价格	LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/HSTL TO HSTL CLOCK DRIVER

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