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MPC860TZQ50D4 PDF预览

MPC860TZQ50D4

更新时间: 2024-02-04 22:35:42
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
78页 529K
描述
PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, 0 to 95C

MPC860TZQ50D4 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357针数:357
Reach Compliance Code:unknown风险等级:5.89
地址总线宽度:32位大小:32
边界扫描:YES最大时钟频率:50 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:YESJESD-30 代码:S-PBGA-B357
JESD-609代码:e0长度:25 mm
低功率模式:YES湿度敏感等级:3
端子数量:357封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):245
认证状态:COMMERCIAL座面最大高度:2.52 mm
速度:50 MHz最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES端子面层:TIN LEAD
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:25 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC

MPC860TZQ50D4 数据手册

 浏览型号MPC860TZQ50D4的Datasheet PDF文件第2页浏览型号MPC860TZQ50D4的Datasheet PDF文件第3页浏览型号MPC860TZQ50D4的Datasheet PDF文件第4页浏览型号MPC860TZQ50D4的Datasheet PDF文件第6页浏览型号MPC860TZQ50D4的Datasheet PDF文件第7页浏览型号MPC860TZQ50D4的Datasheet PDF文件第8页 
Features  
— Up to 8 Kbytes of dual-port RAM  
— 16 serial DMA (SDMA) channels  
— Three parallel I/O registers with open-drain capability  
Four baud-rate generators (BRGs)  
— Independent (can be tied to any SCC or SMC)  
— Allows changes during operation  
— Autobaud support option  
Four serial communications controllers (SCCs)  
— Ethernet/IEEE 802.3® standard optional on SCC1–4, supporting full 10-Mbps operation  
(available only on specially programmed devices)  
— HDLC/SDLC (all channels supported at 2 Mbps)  
— HDLC bus (implements an HDLC-based local area network (LAN))  
— Asynchronous HDLC to support point-to-point protocol (PPP)  
— AppleTalk  
— Universal asynchronous receiver transmitter (UART)  
— Synchronous UART  
— Serial infrared (IrDA)  
— Binary synchronous communication (BISYNC)  
— Totally transparent (bit streams)  
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))  
Two SMCs (serial management channels)  
— UART  
— Transparent  
— General circuit interface (GCI) controller  
— Can be connected to the time-division multiplexed (TDM) channels  
One SPI (serial peripheral interface)  
— Supports master and slave modes  
— Supports multimaster operation on the same bus  
2
One I C (inter-integrated circuit) port  
— Supports master and slave modes  
— Multiple-master environment support  
Time-slot assigner (TSA)  
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation  
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined  
— 1- or 8-bit resolution  
— Allows independent transmit and receive routing, frame synchronization, and clocking  
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9  
Freescale Semiconductor  
5

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