Datasheet > MPC860TZP33

MPC860TZP33

更新时间： 2024-01-14 15:04:10

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	44K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, PBGA357

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MPC860TZP33 技术参数

生命周期：	Active	包装说明：	BGA-357
Reach Compliance Code：	unknown	风险等级：	5.67
地址总线宽度：	32	位大小：	32
边界扫描：	YES	外部数据总线宽度：	32
格式：	FIXED POINT	集成缓存：	YES
JESD-30 代码：	S-PBGA-B357	长度：	25 mm
低功率模式：	YES	DMA 通道数量：	16
外部中断装置数量：	7	端子数量：	357
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA357,19X19,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	座面最大高度：	2.52 mm
速度：	33 MHz	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	25 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC
Base Number Matches：	1

MPC860TZP33 数据手册

MPC860T Architecture Overview

– General circuit interface (GCI) controller

– May be connected to the time-division-multiplexed (TDM) channels

— One SPI (serial peripheral interface)

– Supports master and slave modes

– Supports multimaster operation on the same bus

— One I C (inter-integrated circuit) port

– Supports master and slave modes

– Multimaster environment support

— Time slot assigner

– Allows SCCs and SMCs to run in multiplexed and/or nonmultiplexed operation

– Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user deﬁned

– 1- or 8-bit resolution

– Allows independent transmit and receive routing, frame syncs, clocking

– Allows dynamic changes

– May be internally connected to six serial channels (four SCCs and two SMCs)

— Parallel interface port

– Centronics™ interface support

– Supports fast connection between compatible ports on MPC860 or MC68360

— Low power support

– Full-on–all units fully powered

– Doze–core functional units disabled except time base, decrementer, PLL, memory

controller, RTC, and CPM in low-power standby

– Sleep–all units disabled except RTC and PIT, PLL active for fast wake-up

– Deep sleep–all units disabled including PLL except RTC and PIT

– Low-power STOP mode provides lowest power dissipation

— Debug interface

– Eight comparators: four operate on instruction address, two operate on data address, and

two operate on data

– Supports conditions: = ¹ < >

– Each watchpoint can generate a breakpoint internally

— 3.3-V operation with 5-V TTL compatibility

— 357-pin ball grid array (BGA) package

1.2 MPC860T Architecture Overview

The MPC860T PowerQUICC integrates the embedded MPC860T Core with high-performance, low-power

peripherals to extend the Motorola data communications family of embedded processors into high-end

communications and networking products.

MOTOROLA

MPC860TPowerQUICC™TechnicalSummary

1 2 3 456 7 8...14

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与MPC860TZP33相关器件

型号	品牌	描述	获取价格	数据表
MPC860TZQ50D4	FREESCALE	Hardware Specifications	获取价格
MPC860TZQ50D4	NXP	PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, 0 to 95C	获取价格
MPC860TZQ50D4R2	FREESCALE	Hardware Specifications	获取价格
MPC860TZQ50D4R2	NXP	32-BIT, 50MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357	获取价格
MPC860TZQ66D4	FREESCALE	Hardware Specifications	获取价格
MPC860TZQ66D4	NXP	32-BIT, 66MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357	获取价格

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