Datasheet > MPC860TZP33

MPC860TZP33

更新时间： 2024-02-14 12:09:31

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	44K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, PBGA357

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MPC860TZP33 技术参数

生命周期：	Active	包装说明：	BGA-357
Reach Compliance Code：	unknown	风险等级：	5.67
地址总线宽度：	32	位大小：	32
边界扫描：	YES	外部数据总线宽度：	32
格式：	FIXED POINT	集成缓存：	YES
JESD-30 代码：	S-PBGA-B357	长度：	25 mm
低功率模式：	YES	DMA 通道数量：	16
外部中断装置数量：	7	端子数量：	357
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA357,19X19,50	封装形状：	SQUARE
封装形式：	GRID ARRAY	座面最大高度：	2.52 mm
速度：	33 MHz	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
宽度：	25 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC
Base Number Matches：	1

MPC860TZP33 数据手册

MPC860T PowerQUICC Key Features

– 100-Mbps 802.3 media-independent interface (MII)

– 10-Mbps 802.3 media-independent interface

– 10-Mbps 7-wire interface

— Support for half-duplex 100-Mbps operation (at 33-MHz system clock rate and above)

— Support for full-duplex 100-Mbps operation (at 50-MHz system clock rate and above)

— Large on-chip transmit and receive FIFOs to support a variety of bus latencies

— Retransmission from transmit FIFO following a collision

— Automatic internal ﬂushing of the receive FIFO for runts and collisions

— Off-chip buffer descriptor rings of user-deﬁnable size that allow nearly unlimited ﬂexibility in

management of transmit and receive buffer memory

•

10/100-Mbps media access control (MAC) features

— Address recognition

– Broadcast

– Single station address

– Promiscuous mode

– Multicast hashing

— Full support of the media-independent interface

— Interrupt modes

– Per-frame

– Per-buffer (selectable buffer interrupt functionality using the I bit is not supported)

— Automatic interrupt vector generation for receive and transmit events

Categories: transmit interrupt, receive interrupt, non-time critical interrupt

— Ethernet channel bursts data to/from external memory

Embedded MPC860T Core with 87 MIPS at 66 MHz (using Dhrystone 2.1)

•

— Single-issue, 32-bit version of the embedded MPC860T Core (fully compatible with the

PowerPC user instruction set architecture; refer to the Programming Environments Manual for

32-Bit Implementations of the PowerPC Architecture, REV 2(MPCFPE32B/AD) for more

information) with 32- x 32-bit ﬁxed-point registers

– Embedded core performs branch folding and branch prediction with conditional prefetch,

but without conditional execution

– 4-Kbyte data cache and 4-Kbyte instruction cache, each with an MMU

– Instruction and data caches are two-way, set associative, physical address, 4-word line

burst, least recently used (LRU) replacement, lockable on cache line granularity

– MMUs with 32-entry, fully-associative instruction and data TLBs

– MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and

8 Kbytes; 16 virtual address spaces and 8 protection groups

– Advanced on-chip-emulation debug mode

— Up to 32-bit data bus (dynamic bus sizing of 8, 16, and 32 bits provided through memory

controller)

— 32 address lines

MPC860TPowerQUICC™TechnicalSummary

MOTOROLA

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与MPC860TZP33相关器件

型号	品牌	描述	获取价格	数据表
MPC860TZQ50D4	FREESCALE	Hardware Specifications	获取价格
MPC860TZQ50D4	NXP	PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, 0 to 95C	获取价格
MPC860TZQ50D4R2	FREESCALE	Hardware Specifications	获取价格
MPC860TZQ50D4R2	NXP	32-BIT, 50MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357	获取价格
MPC860TZQ66D4	FREESCALE	Hardware Specifications	获取价格
MPC860TZQ66D4	NXP	32-BIT, 66MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357	获取价格

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