Integrated Communications Processors
MPC8309 PowerQUICC II Pro Processor
Overview
MPC8309 Block Diagram
The MPC8309 processor is part of the entry
level MPC830x communications portfolio based
on the e300 core architecture. It addresses
e300 Core
Complex
the requirements of networking applications,
16/32-bit DDR2
Controller
including I/O cards for low-end base stations,
16 KB
D-Cache
16 KB
I-Cache
low-end Ethernet switches, residential
gateways, modem/routers, industrial control,
factory automation and test and measurement
applications. The MPC830x portfolio extends
current PowerQUICC processor offerings,
delivering an impressive 1.99 DMIPS/MHz
in CPU performance, additional functionality
and faster interfaces while maintaining
Local Bus
QUICC Engine
Coherent System Bus
2 x DUART
I2C, SPI
Up to
3 x RMII/MII
or
4 x
CAN
8-bit
GPIO, Interrupt
Controller
2 x HDLC
/TDM
USB
2.0
eSDHC
8-bit
DMA
PCI
code compatibility with PowerQUICC I
2 x with
and PowerQUICC II processors. MPC830x
processors also provide sub-$10, low power
consumption, a compact board footprint and a
time to market advantage through cost-effective
evaluation kits with optimized BSP and drivers.
IEEE® 1588
Or
16-bit GPIO
Core
Accelerators
I/O
Core Complex
The MPC8309 incorporates the e300c3
with ECC support, 4 x CAN, 4 x UARTs,
High-Speed USB 2.0 controller, enhanced
SDHC controller, a 32-bit peripheral
component interconnect (PCI) controller,
a 16-bit local bus and two direct memory
access controllers (DMAC).
MPC8309 Features
•ꢀ Excellentꢀperformance,ꢀlow-power,ꢀsub-$10ꢀ
(MPC603e-based) core, built on Power
communications processor
®
Architecture technology, which includes 16 KB
•ꢀ Theꢀe300ꢀcore,ꢀbuiltꢀonꢀPowerꢀArchitectureꢀ
technology, with dual integer units enables
more efficient operations to be conducted
in parallel, resulting in a significant
of L1 instruction and data caches, dual integer
units and on-chip memory management units
(MMUs).
In summary, the MPC8309 provides users
with a highly integrated, fully programmable
communications processor helping to ensure
that a cost-effective system solution can be
quickly developed while offering the flexibility
to accommodate new standards and evolving
system requirements.
performance improvement
QUICC Engine Technology
A communications complex based on
•ꢀ Theꢀsingle-RISCꢀQUICCꢀEngineꢀ
communications module offers a future-
proof solution for next-generation designs
by supporting programmable protocol
termination and network interface
termination to meet evolving
QUICC Engine technology forms the heart
of the networking capability of the MPC830x
portfolio. The QUICC Engine block contains
several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided
by the main workhorses of the device—the
unified communication controllers (UCCs).
Each of the five UCCs can support a variety
of communication protocols, including 10/100
Mbps Ethernet and high-level data link control
(HDLC). Two of the UCCs can also support
IEEE® 1588 version-2 time stamping.
protocol standards
•ꢀ DDR2ꢀmemoryꢀcontroller—oneꢀ16/32-bitꢀ
interface at up to 333 MHz with
ECC support
•ꢀ Peripheralꢀinterfacesꢀsuchꢀasꢀ32-bit,ꢀ66ꢀ
MHz PCI, 16-bit, 66 MHz local bus interface
and High-Speed USB 2.0, 4 x CAN, 4 x
UARTs, enhanced SDHC controller
System Interface Unit
The MPC8309 processor also includes a 16/32-
bit double data rate (DDR2) memory controller