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MN1959041

更新时间: 2024-09-20 22:25:27
品牌 Logo 应用领域
松下 - PANASONIC /
页数 文件大小 规格书
23页 206K
描述
COMMERCIAL MPEG-4 VIDEO CODEC IC FOR W-CDMA MOBILE VISUAL TERMINALS

MN1959041 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA,针数:239
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84其他特性:IT ALSO REQUIRES 2.9V SUPPLY
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PBGA-B239
长度:11 mm功能数量:1
端子数量:239最高工作温度:70 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:SQUARE
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.65 V表面贴装:YES
温度等级:OTHER端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
宽度:11 mmBase Number Matches:1

MN1959041 数据手册

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Communication Equipment LSI  
MN1959041  
Commercial MPEG-4 Video Codec IC for W-CDMA Mobile Visual  
Terminals  
Overview  
MN1959041 is an image-processing DSP that adopts a vector pipelined architecture. It provides an extensive set of  
features that allow it to implement the high-efficiency image and video encoding and decoding required for image  
communication, recording, and playback. It implements encoding and decoding that conform to the H.263 and MPEG-  
4 Simple@L1 video encoding standards, and decoding that conforms to the MPEG-4 Simple@L3 video encoding  
standard. It includes dedicated special-purpose circuits for high-speed decoding of the MPEG-4 core profile.  
Features  
General-purpose DSP core (MP: Main Processor) that can implement complex processing flexibly  
Provides an instruction set of 43 instructions, including both scalar and vector instructions.  
Provides interrupt control and task management functions that issue VCE/VIF/MIF (described later) start/stop in-  
structions and DMA transfer instructions.  
Special-purpose arithmetic circuit (VCE: Video Codec Engine) that implements a high-speed video codec  
Integer precision and half-pel precision motion detection circuit (MEF/MEH)  
Discrete cosine transformation/inverse discrete cosine transformation circuits (DCT/IDCT)  
Variable-length encoding and decoding circuits (VLC/VLD)  
Blocking noise elimination circuit (PNR)  
Shape information decoding circuit (CAD)  
Pixel supplementing circuit (PADDING)  
Image synthesis circuit (COMPOSITE)  
Full complement of image signal input and output functions  
Video interface circuit (VIF) that supports both portrait and landscape orientation LCDs  
Support for CIF and QCIF 4:2:2 format video input from CMOS cameras  
P in P function that displays a subscreen in the lower right of the main screen  
Cursor and blue background display functions.  
Mosquito noise elimination filter  
Functions for picture quality adjustment and for combining video and graphics  
IIC (Inter IC) interface (Conforms to Version 2.0, standard and fast mode)  
Video signal format conversion function (YCbCr 4:2:2 RGB; can be stopped when not needed.)  
Graphics overlay function (Either post RGB conversion or post dithering can be selected.)  
Video signal adjustment functions: outline enhancement, tint, color gain, brightness, contrast, and gamma adjust-  
ment  
Dithering function for pseudo 24-bit color (2 × 2 matrix)  
Monochrome conversion function (Either monochrome or sepia can be specified.)  
Allows moving the display area (a 176-pixel × 220-line area placed anywhere within a 352-pixel × 288-line image)  
YCbCr 4:2:2 test image generation function (75% color bar, horizontal/vertical stripe, arbitrary brightness/color  
difference)  
Camera reset control function  
Large on-chip DRAM capacity  
On-chip 20 Mbit DRAM provided to reduce parts counts and achieve overall system cost reductions  
Publication date: November 2002  
SDM00008AEM  
1

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