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MM74HCT688J PDF预览

MM74HCT688J

更新时间: 2024-11-23 13:11:39
品牌 Logo 应用领域
美国国家半导体 - NSC 比较器
页数 文件大小 规格书
4页 106K
描述
IC HCT SERIES, 8-BIT IDENTITY COMPARATOR, INVERTED OUTPUT, CDIP20, DIP-20, Arithmetic Circuit

MM74HCT688J 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP-20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N其他特性:CASCADABLE
系列:HCTJESD-30 代码:R-GDIP-T20
JESD-609代码:e0长度:24.51 mm
负载电容(CL):50 pF逻辑集成电路类型:IDENTITY COMPARATOR
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):44 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM74HCT688J 数据手册

 浏览型号MM74HCT688J的Datasheet PDF文件第2页浏览型号MM74HCT688J的Datasheet PDF文件第3页浏览型号MM74HCT688J的Datasheet PDF文件第4页 
February 1988  
MM54HCT688/MM74HCT688  
8-Bit Magnitude Comparator (Equality Detector)  
General Description  
This equality detector utilizes advanced silicon-gate CMOS  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
devices. These parts are also plug in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
technology to compare bit for bit two 8-bit words and indi-  
e
cate whether or not they are equal. The P Q output indi-  
cates equality when it is low. A single active low enable is  
provided to facilitate cascading of several packages and en-  
able comparison of words greater than 8 bits.  
All inputs are protected from damage due to static dis-  
charge by diodes to V  
This device is useful in memory block decoding applica-  
tions, where memory block enable signals must be generat-  
ed from computer address information.  
and ground.  
CC  
Features  
Y
The comparator combines the low power consumption of  
CMOS, but inputs are compatible with TTL logic levels, and  
the output can drive 10 low power Schottky equivalent  
loads.  
TTL input compatible  
Y
Y
Y
Y
Typical propagation delay: 20 ns  
Low quiescent current: 80 mA maximum (74HCT Series)  
Large output current: 4 mA  
Same as HCT521  
Logic Diagrams  
TL/F/5371–2  
C
1995 National Semiconductor Corporation  
TL/F/5371  
RRD-B30M105/Printed in U. S. A.  

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